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Searched refs:VSELECT (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp170 setOperationAction(ISD::VSELECT, P, Custom); in initializeHVXLowering()
306 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
439 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
2186 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru); in LowerHvxMaskedOp()
2472 SDValue Mux = DAG.getNode(ISD::VSELECT, dl, IntTy, {Eq, Tmp5, Tmp4}); in emitHvxShiftRightRnd()
2592 SDValue X0 = DAG.getNode(ISD::VSELECT, dl, VecTy, {Q0, B, Zero}); in emitHvxMulLoHiV60()
2810 SDValue Bnd = DAG.getNode(ISD::VSELECT, dl, ResTy, {Neg, M80, M7F}); in ExpandHvxFpToInt()
2813 SDValue Frc14 = DAG.getNode(ISD::VSELECT, dl, ResTy, {Neg, Frc13, Frc02}); in ExpandHvxFpToInt()
2814 Int = DAG.getNode(ISD::VSELECT, dl, ResTy, {Pos, Frc14, Bnd}); in ExpandHvxFpToInt()
2818 SDValue Frc23 = DAG.getNode(ISD::VSELECT, d in ExpandHvxFpToInt()
[all...]
H A DHexagonISelLowering.cpp1777 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1778 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1846 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
3396 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3510 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3518 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def122 ADD_VVP_OP(VVP_SELECT,VSELECT) REGISTER_PACKED(VVP_SELECT)
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp102 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
160 setTargetDAGCombine({ISD::AND, ISD::OR, ISD::SRA, ISD::VSELECT, ISD::XOR}); in MipsSETargetLowering()
349 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
394 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
710 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1045 case ISD::VSELECT: in PerformDAGCombine()
1613 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1628 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1633 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1636 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h764 VSELECT, enumerator
H A DSelectionDAG.h1264 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
H A DBasicTTIImpl.h1244 ISD = ISD::VSELECT;
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-tqma8mpql.dtsi160 /* VCC SD IO - switched using SD2 VSELECT */
H A Dimx8mn-tqma8mqnl.dtsi195 /* VCC SD IO - switched using SD2 VSELECT */
H A Dimx8mm-tqma8mqml.dtsi204 /* VCC SD IO - switched using SD2 VSELECT */
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul-14x14-evk.dtsi606 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
H A Dimx7-mba7.dtsi529 /* VSELECT */
H A Dimx7d-sdb.dts757 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp70 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
773 case ISD::VSELECT: in ScalarizeVectorOperand()
1076 case ISD::VSELECT: in SplitVectorResult()
3173 case ISD::VSELECT: in SplitVectorOperand()
3298 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?"); in SplitVecOp_VSELECT()
3315 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
3317 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
4335 case ISD::VSELECT: in WidenVectorResult()
6012 // and if needed adjusting the mask vector type to match that of the VSELECT. in WidenVSELECTMask()
6019 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTMask()
[all...]
H A DSelectionDAGDumper.cpp322 case ISD::VSELECT: return "vselect"; in getOperationName()
H A DLegalizeVectorOps.cpp384 case ISD::VSELECT: in LegalizeOp()
875 case ISD::VSELECT: in Expand()
H A DTargetLowering.cpp1678 case ISD::VSELECT: in SimplifyDemandedBits()
3410 case ISD::VSELECT: { in SimplifyDemandedVectorElts()
6887 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { in prepareUREMEqFold()
6892 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, in prepareUREMEqFold()
7166 !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) in prepareSREMEqFold()
7192 SDValue Blended = DAG.getNode(ISD::VSELECT, DL, SETCCVT, DivisorIsIntMin, in prepareSREMEqFold()
7499 case ISD::VSELECT: { in getNegatedExpression()
8497 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandFMINIMUM_FMAXIMUM()
10279 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandIntMINMAX()
10369 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandAddSubSat()
[all …]
H A DSelectionDAG.cpp3538 case ISD::VSELECT: in computeKnownBits()
4408 if (Val.getOpcode() == ISD::SELECT || Val.getOpcode() == ISD::VSELECT) in isKnownToBeAPowerOfTwo()
4663 case ISD::VSELECT: in ComputeNumSignBits()
5536 case ISD::VSELECT: in isKnownNeverZero()
7479 case ISD::VSELECT: in getNode()
12449 case ISD::VSELECT: in UnrollVectorOp()
H A DDAGCombiner.cpp1903 case ISD::VSELECT: return visitVSELECT(N); in visit()
2393 if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse()) in foldSelectWithIdentityConstant()
5577 case ISD::VSELECT: in isSaturatingMinMax()
11499 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT || in foldBoolSelectToLogic()
12831 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
12852 (N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes && in tryToFoldExtendSelectLoad()
12853 TLI.getOperationAction(ISD::VSELECT, VT) != TargetLowering::Legal)) in tryToFoldExtendSelectLoad()
13220 if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in matchVSelectOpSizesWithSetCC()
13224 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
13247 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); in matchVSelectOpSizesWithSetCC()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def760 VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT)
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp201 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
412 setOperationAction(ISD::VSELECT, VT, Legal); in addMVEVectorTypes()
465 setOperationAction(ISD::VSELECT, VT, Expand); in addMVEVectorTypes()
1603 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
8617 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes); in PromoteMVEPredVector()
10286 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru); in LowerMLOAD()
13330 } else if (N->getOpcode() == ISD::VSELECT) { in PerformVQDMULHCombine()
13463 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS); in PerformVSELECTCombine()
16972 if (Op0.getOpcode() == ISD::VSELECT && Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
16975 if (Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1055 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); in X86TargetLowering()
1173 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1180 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1366 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in X86TargetLowering()
1646 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1664 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in X86TargetLowering()
1740 setOperationAction(ISD::VSELECT, VT, Expand); in X86TargetLowering()
2007 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
2136 setOperationAction(ISD::VSELECT, VT, Expand); in X86TargetLowering()
2204 setOperationAction(ISD::VSELECT, VT, Legal); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp762 {ISD::SELECT_CC, ISD::VSELECT, ISD::VP_MERGE, ISD::VP_SELECT}, VT, in RISCVTargetLowering()
1253 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
1319 {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT, in RISCVTargetLowering()
1349 {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT, in RISCVTargetLowering()
1381 setOperationAction({ISD::VSELECT, ISD::SELECT}, VT, Custom); in RISCVTargetLowering()
3601 // Blend in all instances of this value using a VSELECT, using a in lowerBuildVectorViaDominantValues()
3608 Vec = DAG.getNode(ISD::VSELECT, DL, VT, in lowerBuildVectorViaDominantValues()
4145 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, SubVecA, SubVecB); in lowerBUILD_VECTOR()
5376 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); in lowerVECTOR_SHUFFLE()
5377 return DAG.getNode(ISD::VSELECT, D in lowerVECTOR_SHUFFLE()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1111 setTargetDAGCombine({ISD::SELECT, ISD::VSELECT}); in AArch64TargetLowering()
1880 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
2122 setOperationAction(ISD::VSELECT, VT, Default); in addTypeForFixedLengthSVE()
7008 case ISD::VSELECT: in LowerOperation()
10722 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
10733 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
14646 return DAG.getNode(ISD::VSELECT, DL, VT, PTrue, ScalableVec1, Vec0); in LowerINSERT_SUBVECTOR()
21504 return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
23823 if (FirstUse->getOpcode() != ISD::VSELECT) in tryToWidenSetCCOperands()
23829 return N->getOpcode() != ISD::VSELECT || N->getValueType(0) != UseMVT; in tryToWidenSetCCOperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp542 ISD::USHLSAT, ISD::USUBO, ISD::USUBO_CARRY, ISD::VSELECT, in NVPTXTargetLowering()
733 ISD::VSELECT}); in NVPTXTargetLowering()
6044 case ISD::VSELECT: in PerformDAGCombine()

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