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Searched refs:VSELECT (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp172 setOperationAction(ISD::VSELECT, P, Custom); in initializeHVXLowering()
312 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
449 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
2223 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru); in LowerHvxMaskedOp()
2509 SDValue Mux = DAG.getNode(ISD::VSELECT, dl, IntTy, {Eq, Tmp5, Tmp4}); in emitHvxShiftRightRnd()
2629 SDValue X0 = DAG.getNode(ISD::VSELECT, dl, VecTy, {Q0, B, Zero}); in emitHvxMulLoHiV60()
2847 SDValue Bnd = DAG.getNode(ISD::VSELECT, dl, ResTy, {Neg, M80, M7F}); in ExpandHvxFpToInt()
2850 SDValue Frc14 = DAG.getNode(ISD::VSELECT, dl, ResTy, {Neg, Frc13, Frc02}); in ExpandHvxFpToInt()
2851 Int = DAG.getNode(ISD::VSELECT, dl, ResTy, {Pos, Frc14, Bnd}); in ExpandHvxFpToInt()
2855 SDValue Frc23 = DAG.getNode(ISD::VSELECT, dl, ResTy, Rsn, M7F, Frc02); in ExpandHvxFpToInt()
[all …]
H A DHexagonISelLowering.cpp1851 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1852 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1920 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
3418 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3532 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3540 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def122 ADD_VVP_OP(VVP_SELECT,VSELECT) REGISTER_PACKED(VVP_SELECT)
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp141 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
199 setTargetDAGCombine({ISD::AND, ISD::OR, ISD::SRA, ISD::VSELECT, ISD::XOR}); in MipsSETargetLowering()
388 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
433 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
749 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1084 case ISD::VSELECT: in PerformDAGCombine()
1657 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1672 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1677 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1680 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-tqma8mpql.dtsi162 /* VCC SD IO - switched using SD2 VSELECT */
H A Dimx8mn-tqma8mqnl.dtsi200 /* VCC SD IO - switched using SD2 VSELECT */
H A Dimx8mm-tqma8mqml.dtsi205 /* VCC SD IO - switched using SD2 VSELECT */
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h787 VSELECT, enumerator
H A DSDPatternMatch.h558 return TernaryOpc_match<T0_P, T1_P, T2_P>(ISD::VSELECT, Cond, T, F);
674 sd_context_match(N, Ctx, m_Opc(ISD::VSELECT))) {
H A DSelectionDAG.h1342 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul-14x14-evk.dtsi638 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
H A Dimx7-mba7.dtsi502 /* VSELECT */
H A Dimx7d-sdb.dts789 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp71 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
786 case ISD::VSELECT: in ScalarizeVectorOperand()
1123 case ISD::VSELECT: in SplitVectorResult()
2550 DAG.getNode(ISD::VSELECT, DL, VecVT, Mask, Compressed, Passthru); in SplitVecRes_VECTOR_COMPRESS()
3445 case ISD::VSELECT: in SplitVectorOperand()
3603 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
3605 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
4695 case ISD::VSELECT: in WidenVectorResult()
6461 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTMask()
6834 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break; in WidenVectorOperand()
H A DSelectionDAGDumper.cpp339 case ISD::VSELECT: return "vselect"; in getOperationName()
H A DTargetLowering.cpp1725 case ISD::VSELECT: in SimplifyDemandedBits()
3551 case ISD::VSELECT: { in SimplifyDemandedVectorElts()
7115 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { in prepareUREMEqFold()
7120 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, in prepareUREMEqFold()
7396 !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) in prepareSREMEqFold()
7422 SDValue Blended = DAG.getNode(ISD::VSELECT, DL, SETCCVT, DivisorIsIntMin, in prepareSREMEqFold()
7718 case ISD::VSELECT: { in getNegatedExpression()
8631 !isOperationLegalOrCustom(ISD::VSELECT, VT)) && in createSelectForFMINNUM_FMAXNUM()
8730 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandFMINIMUM_FMAXIMUM()
8818 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandFMINIMUMNUM_FMAXIMUMNUM()
[all …]
H A DLegalizeVectorOps.cpp395 case ISD::VSELECT: in LegalizeOp()
957 case ISD::VSELECT: in Expand()
H A DSelectionDAG.cpp3781 case ISD::VSELECT: in computeKnownBits()
4679 if (Val.getOpcode() == ISD::SELECT || Val.getOpcode() == ISD::VSELECT) in isKnownToBeAPowerOfTwo()
4934 case ISD::VSELECT: in ComputeNumSignBits()
5618 case ISD::VSELECT: in canCreateUndefOrPoison()
5933 case ISD::VSELECT: in isKnownNeverZero()
8011 case ISD::VSELECT: in getNode()
13019 case ISD::VSELECT: in UnrollVectorOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp808 setOperationAction({ISD::SELECT_CC, ISD::VSELECT, ISD::VP_SELECT}, VT, in RISCVTargetLowering()
1372 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
1452 {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT, in RISCVTargetLowering()
1492 {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT, in RISCVTargetLowering()
1524 setOperationAction({ISD::VSELECT, ISD::SELECT}, VT, Custom); in RISCVTargetLowering()
1657 ISD::VSELECT, ISD::VECREDUCE_ADD}); in RISCVTargetLowering()
2181 if (SelectOpcode != ISD::VSELECT) in shouldFoldSelectWithIdentityConstant()
3922 Vec = DAG.getNode(ISD::VSELECT, DL, VT, in lowerBuildVectorViaDominantValues()
4426 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, SubVecA, SubVecB); in lowerBUILD_VECTOR()
4902 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, Splat, V1); in lowerVECTOR_SHUFFLEAsVRGatherVX()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def721 VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT)
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp206 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
422 setOperationAction(ISD::VSELECT, VT, Legal); in addMVEVectorTypes()
475 setOperationAction(ISD::VSELECT, VT, Expand); in addMVEVectorTypes()
1596 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
8669 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes); in PromoteMVEPredVector()
10335 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru); in LowerMLOAD()
13397 } else if (N->getOpcode() == ISD::VSELECT) { in PerformVQDMULHCombine()
13530 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS); in PerformVSELECTCombine()
13959 SelectOpcode == ISD::VSELECT; in shouldFoldSelectWithIdentityConstant()
17045 if (Op0.getOpcode() == ISD::VSELECT && Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp653 ISD::USHLSAT, ISD::USUBO, ISD::USUBO_CARRY, ISD::VSELECT, in NVPTXTargetLowering()
667 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand); in NVPTXTargetLowering()
842 ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, ISD::VSELECT, in NVPTXTargetLowering()
5825 case ISD::VSELECT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1070 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); in X86TargetLowering()
1194 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1201 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1387 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in X86TargetLowering()
1670 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1688 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in X86TargetLowering()
1769 setOperationAction(ISD::VSELECT, VT, Expand); in X86TargetLowering()
2040 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
2199 setOperationAction(ISD::VSELECT, VT, Expand); in X86TargetLowering()
2268 setOperationAction(ISD::VSELECT, VT, Legal); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1153 setTargetDAGCombine({ISD::SELECT, ISD::VSELECT}); in AArch64TargetLowering()
2049 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
2359 setOperationAction(ISD::VSELECT, VT, Default); in addTypeForFixedLengthSVE()
4829 return DAG.getNode(ISD::VSELECT, DL, VT, In, TrueVal, FalseVal); in LowerVectorINT_TO_FP()
6995 DAG.getNode(ISD::VSELECT, DL, VecVT, IndexMask, Compressed, Passthru); in LowerVECTOR_COMPRESS()
7480 case ISD::VSELECT: in LowerOperation()
11550 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
11561 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
15549 return DAG.getNode(ISD::VSELECT, DL, VT, PTrue, ScalableVec1, Vec0); in LowerINSERT_SUBVECTOR()
18015 SelectOpcode == ISD::VSELECT; in shouldFoldSelectWithIdentityConstant()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp292 setOperationAction(ISD::VSELECT, VT, Legal); in LoongArchTargetLowering()
360 setOperationAction(ISD::VSELECT, VT, Legal); in LoongArchTargetLowering()
4532 case ISD::VSELECT: in checkBitcastSrcVectorSize()
4560 case ISD::VSELECT: in signExtendBitcastSrcVector()

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