Lines Matching refs:VSELECT
1678 case ISD::VSELECT: in SimplifyDemandedBits()
3410 case ISD::VSELECT: { in SimplifyDemandedVectorElts()
6887 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { in prepareUREMEqFold()
6892 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, in prepareUREMEqFold()
7166 !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) in prepareSREMEqFold()
7192 SDValue Blended = DAG.getNode(ISD::VSELECT, DL, SETCCVT, DivisorIsIntMin, in prepareSREMEqFold()
7499 case ISD::VSELECT: { in getNegatedExpression()
8497 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandFMINIMUM_FMAXIMUM()
10279 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandIntMINMAX()
10369 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandAddSubSat()
10490 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandShlSat()