Lines Matching refs:VSELECT
1111 setTargetDAGCombine({ISD::SELECT, ISD::VSELECT}); in AArch64TargetLowering()
1880 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
2122 setOperationAction(ISD::VSELECT, VT, Default); in addTypeForFixedLengthSVE()
7008 case ISD::VSELECT: in LowerOperation()
10722 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
10733 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
14646 return DAG.getNode(ISD::VSELECT, DL, VT, PTrue, ScalableVec1, Vec0); in LowerINSERT_SUBVECTOR()
21504 return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
23823 if (FirstUse->getOpcode() != ISD::VSELECT) in tryToWidenSetCCOperands()
23829 return N->getOpcode() != ISD::VSELECT || N->getValueType(0) != UseMVT; in tryToWidenSetCCOperands()
24193 return DAG.getNode(ISD::VSELECT, SDLoc(N), NTy, in trySwapVSelectOperands()
24265 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
25335 case ISD::VSELECT: in PerformDAGCombine()
27764 auto ScalableRes = DAG.getNode(ISD::VSELECT, DL, ContainerVT, in LowerFixedLengthVectorSelectToSVE()