Home
last modified time | relevance | path

Searched refs:VE (Results 1 – 25 of 96) sorted by relevance

1234

/freebsd/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp59 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
60 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
61 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
62 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
63 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
64 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
65 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
66 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
67 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
68 VE::SW63};
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEMCAsmInfo.cpp22 {VE::S_HI32, "hi"},
23 {VE::S_LO32, "lo"},
24 {VE::S_PC_HI32, "pc_hi"},
25 {VE::S_PC_LO32, "pc_lo"},
26 {VE::S_GOT_HI32, "got_hi"},
27 {VE::S_GOT_LO32, "got_lo"},
28 {VE::S_GOTOFF_HI32, "gotoff_hi"},
29 {VE::S_GOTOFF_LO32, "gotoff_lo"},
30 {VE::S_PLT_HI32, "plt_hi"},
31 {VE::S_PLT_LO32, "plt_lo"},
[all …]
H A DVEAsmBackend.cpp31 case VE::fixup_ve_hi32: in adjustFixupValue()
32 case VE::fixup_ve_pc_hi32: in adjustFixupValue()
33 case VE::fixup_ve_got_hi32: in adjustFixupValue()
34 case VE::fixup_ve_gotoff_hi32: in adjustFixupValue()
35 case VE::fixup_ve_plt_hi32: in adjustFixupValue()
36 case VE::fixup_ve_tls_gd_hi32: in adjustFixupValue()
37 case VE::fixup_ve_tpoff_hi32: in adjustFixupValue()
39 case VE::fixup_ve_reflong: in adjustFixupValue()
40 case VE::fixup_ve_srel32: in adjustFixupValue()
41 case VE::fixup_ve_lo32: in adjustFixupValue()
[all …]
H A DVEELFObjectWriter.cpp43 case VE::S_TLS_GD_HI32: in getRelocType()
44 case VE::S_TLS_GD_LO32: in getRelocType()
45 case VE::S_TPOFF_HI32: in getRelocType()
46 case VE::S_TPOFF_LO32: in getRelocType()
54 if (SExpr->getSpecifier() == VE::S_PC_LO32) in getRelocType()
77 case VE::fixup_ve_reflong: in getRelocType()
78 case VE::fixup_ve_srel32: in getRelocType()
80 case VE::fixup_ve_pc_hi32: in getRelocType()
82 case VE::fixup_ve_pc_lo32: in getRelocType()
101 case VE::fixup_ve_reflong: in getRelocType()
[all …]
H A DVEMCCodeEmitter.cpp83 case VE::fixup_ve_srel32: in addFixup()
84 case VE::fixup_ve_pc_hi32: in addFixup()
85 case VE::fixup_ve_pc_lo32: in addFixup()
114 auto Kind = VE::getFixupKind(SExpr->getSpecifier()); in getMachineOpValue()
135 addFixup(Fixups, 0, MO.getExpr(), VE::fixup_ve_srel32); in getBranchTargetOpValue()
H A DVEMCAsmInfo.h35 namespace VE {
56 VE::Fixups getFixupKind(uint8_t S);
H A DVEInstPrinter.cpp33 unsigned AltIdx = VE::AsmName; in printRegName()
35 if (MRI.getRegClass(VE::MISCRegClassID).contains(Reg)) in printRegName()
36 AltIdx = VE::NoRegAltName; in printRegName()
H A DVEMCTargetDesc.cpp40 unsigned Reg = MRI.getDwarfRegNum(VE::SX11, true); in createVEMCAsmInfo()
54 InitVEMCRegisterInfo(X, VE::SX10); in createVEMCRegisterInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp77 const MCExpr *extractSpecifier(const MCExpr *E, VE::Specifier &Variant);
98 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
99 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
100 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
101 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
102 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
103 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
104 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
105 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
106 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp149 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
150 .addReg(VE::SX11) in emitPrologueInsns()
153 .addReg(VE::SX9); in emitPrologueInsns()
154 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
155 .addReg(VE::SX11) in emitPrologueInsns()
158 .addReg(VE::SX10); in emitPrologueInsns()
161 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
162 .addReg(VE::SX11) in emitPrologueInsns()
165 .addReg(VE::SX15); in emitPrologueInsns()
166 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
[all …]
H A DVEInstrInfo.cpp38 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} in VEInstrInfo()
97 using namespace llvm::VE; in isUncondBranchOpcode()
112 using namespace llvm::VE; in isCondBranchOpcode()
124 using namespace llvm::VE; in isIndirectBranchOpcode()
237 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
253 opc[0] = VE::BRCFWir; in insertBranch()
254 opc[1] = VE::BRCFWrr; in insertBranch()
256 opc[0] = VE::BRCFLir; in insertBranch()
257 opc[1] = VE::BRCFLrr; in insertBranch()
261 opc[0] = VE::BRCFSir; in insertBranch()
[all …]
H A DVERegisterInfo.cpp32 VERegisterInfo::VERegisterInfo() : VEGenRegisterInfo(VE::SX10) {} in VERegisterInfo()
66 VE::SX8, // Stack limit in getReservedRegs()
67 VE::SX9, // Frame pointer in getReservedRegs()
68 VE::SX10, // Link register (return address) in getReservedRegs()
69 VE::SX11, // Stack pointer in getReservedRegs()
72 VE::SX12, // Outer register in getReservedRegs()
73 VE::SX13, // Id register for dynamic linker in getReservedRegs()
75 VE::SX14, // Thread pointer in getReservedRegs()
76 VE::SX15, // Global offset table register in getReservedRegs()
77 VE::SX16, // Procedure linkage table register in getReservedRegs()
[all …]
H A DVEFrameLowering.h59 {VE::SX17, 40}, {VE::SX18, 48}, {VE::SX19, 56}, {VE::SX20, 64}, in getCalleeSavedSpillSlots()
60 {VE::SX21, 72}, {VE::SX22, 80}, {VE::SX23, 88}, {VE::SX24, 96}, in getCalleeSavedSpillSlots()
61 {VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128}, in getCalleeSavedSpillSlots()
62 {VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160}, in getCalleeSavedSpillSlots()
63 {VE::SX33, 168}}; in getCalleeSavedSpillSlots()
H A DVEAsmPrinter.cpp71 static MCOperand createVEMCOperand(VE::Specifier Kind, MCSymbol *Sym, in createVEMCOperand()
78 static MCOperand createGOTRelExprOp(VE::Specifier Kind, MCSymbol *GOTLabel, in createGOTRelExprOp()
87 SICInst.setOpcode(VE::SIC); in emitSIC()
95 BSICInst.setOpcode(VE::BSICrii); in emitBSIC()
107 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi()
119 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi()
131 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii()
144 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri()
165 emitBinary(OutStreamer, VE::ANDrm, RS1, Imm, RD, STI); in emitANDrm()
169 VE::Specifier HiKind, VE::Specifier LoKind, MCOperand &RD, in emitHiLo()
[all …]
H A DVEISelLowering.cpp85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses()
86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses()
87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses()
88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses()
89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses()
93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses()
95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
413 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerReturn()
490 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerFormalArguments()
[all …]
H A DVERegisterInfo.td1 //===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===//
10 // Declarations that describe the VE register file
18 let Namespace = "VE";
26 let Namespace = "VE";
34 let Namespace = "VE";
44 let Namespace = "VE";
49 let Namespace = "VE" in {
77 def MISC : RegisterClass<"VE", [i64], 64,
95 def VLS : RegisterClass<"VE", [i32], 64, (add VL)>;
173 def I32 : RegisterClass<"VE", [i32], 32,
[all …]
H A DVE.td1 //===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
19 // VE Subtarget features.
36 // Use both VE register name matcher to accept "S0~S63" register names
43 // VE processors supported.
61 def VE : Target {
H A DVECallingConv.td1 //===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===//
9 // This describes the calling conventions for the VE architectures.
14 // Aurora VE
24 ///// C Calling Convention (VE ABI v2.1) /////
26 // Reference: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-ABI_v2.1.pdf
58 ///// Standard vararg C Calling Convention (VE ABI v2.1) /////
H A DLVLGen.cpp55 return VE::NoRegister; in getVL()
76 if (Reg != VE::NoRegister) { in runOnMachineBasicBlock()
89 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(VE::LVLr)).addReg(Reg); in runOnMachineBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Bitcode/Writer/
H A DBitcodeWriter.cpp195 ValueEnumerator VE; member in __anoneb218b5c0111::ModuleBitcodeWriterBase
220 VE(M, ShouldPreserveUseListOrder), Index(Index) { in ModuleBitcodeWriterBase()
226 GlobalValueId = VE.getValues().size(); in ModuleBitcodeWriterBase()
283 return VE.getValueID(VI.getValue()); in getValueId()
997 VE.getAttributeGroups(); in writeAttributeGroupTable()
1006 Record.push_back(VE.getAttributeGroupID(Pair)); in writeAttributeGroupTable()
1040 Record.push_back(VE.getTypeID(Attr.getValueAsType())); in writeAttributeGroupTable()
1066 const std::vector<AttributeList> &Attrs = VE.getAttributeLists(); in writeAttributeTable()
1076 Record.push_back(VE.getAttributeGroupID({i, AS})); in writeAttributeTable()
1088 const ValueEnumerator::TypeList &TypeList = VE.getTypes(); in writeTypeTable()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/DXILWriter/
H A DDXILBitcodeWriter.cpp107 ValueEnumerator VE; member in llvm::dxil::DXILBitcodeWriter
137 StrtabBuilder(StrtabBuilder), M(M), VE(M, I8PtrTy), Buffer(Buffer), in DXILBitcodeWriter()
140 GlobalValueId = VE.getValues().size(); in DXILBitcodeWriter()
143 VE.EnumerateType(El.second); in DXILBitcodeWriter()
201 return VE.getValueID(VI.getValue()); in getValueId()
528 return VE.getTypeID(T); in getTypeID()
531 return VE.getTypeID(It->second); in getTypeID()
537 return VE.getTypeID(T); in getTypeID()
538 return VE.getTypeID(I8PtrTy); in getTypeID()
546 return VE.getTypeID(PtrTy->getElementType()); in getGlobalObjectValueTypeID()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Daspeed-video.txt3 The Video Engine (VE) embedded in the Aspeed AST2400/2500/2600 SOCs can
10 - reg: contains the offset and length of the VE memory region
12 the VE (ordering must match the clock-names property)
15 the VE
16 - interrupts: the interrupt associated with the VE on this platform
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DVE.def8 // - System V Application Binary Interface - VE Architecture
10 // - ELF Handling For Thread-Local Storage - VE Architecture
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsVE.def1 //===--- BuiltinsVE.def - VE Builtin function database ----------*- C++ -*-===//
9 // This file defines the VE-specific builtin function database. Users of
/freebsd/contrib/llvm-project/clang/lib/Serialization/
H A DASTWriter.cpp7969 for (Expr *VE : C->varlist()) in VisitOMPInitClause()
7970 Record.AddStmt(VE); in VisitOMPInitClause()
8015 for (auto *VE : C->varlist()) { in VisitOMPPrivateClause() local
8016 Record.AddStmt(VE); in VisitOMPPrivateClause()
8018 for (auto *VE : C->private_copies()) { in VisitOMPPrivateClause() local
8019 Record.AddStmt(VE); in VisitOMPPrivateClause()
8027 for (auto *VE : C->varlist()) { in VisitOMPFirstprivateClause() local
8028 Record.AddStmt(VE); in VisitOMPFirstprivateClause()
8030 for (auto *VE : C->private_copies()) { in VisitOMPFirstprivateClause() local
8031 Record.AddStmt(VE); in VisitOMPFirstprivateClause()
[all …]

1234