1480093f4SDimitry Andric//===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===// 2480093f4SDimitry Andric// 3480093f4SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4480093f4SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5480093f4SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6480093f4SDimitry Andric// 7480093f4SDimitry Andric//===----------------------------------------------------------------------===// 8480093f4SDimitry Andric// 9480093f4SDimitry Andric// 10480093f4SDimitry Andric//===----------------------------------------------------------------------===// 11480093f4SDimitry Andric 12480093f4SDimitry Andric//===----------------------------------------------------------------------===// 13480093f4SDimitry Andric// Target-independent interfaces which we are implementing 14480093f4SDimitry Andric//===----------------------------------------------------------------------===// 15480093f4SDimitry Andric 16480093f4SDimitry Andricinclude "llvm/Target/Target.td" 17480093f4SDimitry Andric 18480093f4SDimitry Andric//===----------------------------------------------------------------------===// 19480093f4SDimitry Andric// VE Subtarget features. 20480093f4SDimitry Andric// 21e8d8bef9SDimitry Andricdef FeatureEnableVPU 22e8d8bef9SDimitry Andric : SubtargetFeature<"vpu", "EnableVPU", "true", 23e8d8bef9SDimitry Andric "Enable the VPU">; 24480093f4SDimitry Andric 25480093f4SDimitry Andric//===----------------------------------------------------------------------===// 26480093f4SDimitry Andric// Register File, Calling Conv, Instruction Descriptions 27480093f4SDimitry Andric//===----------------------------------------------------------------------===// 28480093f4SDimitry Andric 29480093f4SDimitry Andricinclude "VERegisterInfo.td" 30480093f4SDimitry Andricinclude "VECallingConv.td" 31480093f4SDimitry Andricinclude "VEInstrInfo.td" 32480093f4SDimitry Andric 3306c3fb27SDimitry Andricdef VEInstrInfo : InstrInfo {} 34480093f4SDimitry Andric 355ffd83dbSDimitry Andricdef VEAsmParser : AsmParser { 365ffd83dbSDimitry Andric // Use both VE register name matcher to accept "S0~S63" register names 375ffd83dbSDimitry Andric // and default register matcher to accept other registeres. 385ffd83dbSDimitry Andric let AllowDuplicateRegisterNames = 1; 395ffd83dbSDimitry Andric let ShouldEmitMatchRegisterAltName = 1; 405ffd83dbSDimitry Andric} 415ffd83dbSDimitry Andric 42480093f4SDimitry Andric//===----------------------------------------------------------------------===// 43480093f4SDimitry Andric// VE processors supported. 44480093f4SDimitry Andric//===----------------------------------------------------------------------===// 45480093f4SDimitry Andric 46480093f4SDimitry Andricclass Proc<string Name, list<SubtargetFeature> Features> 47480093f4SDimitry Andric : Processor<Name, NoItineraries, Features>; 48480093f4SDimitry Andric 49*5f757f3fSDimitry Andricdef : Proc<"generic", [FeatureEnableVPU]>; 50480093f4SDimitry Andric 51480093f4SDimitry Andric//===----------------------------------------------------------------------===// 52480093f4SDimitry Andric// Declare the target which we are implementing 53480093f4SDimitry Andric//===----------------------------------------------------------------------===// 54480093f4SDimitry Andric 55480093f4SDimitry Andricdef VEAsmWriter : AsmWriter { 56480093f4SDimitry Andric string AsmWriterClassName = "InstPrinter"; 57480093f4SDimitry Andric int PassSubtarget = 1; 58480093f4SDimitry Andric int Variant = 0; 59480093f4SDimitry Andric} 60480093f4SDimitry Andric 61480093f4SDimitry Andricdef VE : Target { 62480093f4SDimitry Andric // Pull in Instruction Info: 63480093f4SDimitry Andric let InstructionSet = VEInstrInfo; 645ffd83dbSDimitry Andric let AssemblyParsers = [VEAsmParser]; 65480093f4SDimitry Andric let AssemblyWriters = [VEAsmWriter]; 66480093f4SDimitry Andric let AllowRegisterRenaming = 1; 67480093f4SDimitry Andric} 68