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Searched refs:SMIN (Results 1 – 25 of 40) sorted by relevance

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/freebsd/usr.bin/calendar/
H A Dsunpos.c188 #define SMIN(s) (((s) % 3600) / 60) macro
244 SHOUR(dial), SMIN(dial), SSEC(dial), in fequinoxsolstice()
283 SHOUR(dial), SMIN(dial), SSEC(dial), in fequinoxsolstice()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3751 { ISD::SMIN, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3752 { ISD::SMIN, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3829 { ISD::SMIN, MVT::v8i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3830 { ISD::SMIN, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3831 { ISD::SMIN, MVT::v32i16, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3832 { ISD::SMIN, MVT::v64i8, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3833 { ISD::SMIN, MVT::v4i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3834 { ISD::SMIN, MVT::v2i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3992 { ISD::SMIN, MVT::v2i64, { 2, 7, 2, 3 } }, in getIntrinsicInstrCost()
3993 { ISD::SMIN, MVT::v4i64, { 2, 7, 2, 3 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h718 SMIN, enumerator
H A DSDPatternMatch.h807 return BinaryOpc_match<LHS, RHS, true>(ISD::SMIN, L, R);
812 return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::SMIN, L, R),
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1960 {ISD::SMIN, MVT::v16i8, 4}, in getMinMaxReductionCost()
1961 {ISD::SMIN, MVT::v8i16, 3}, in getMinMaxReductionCost()
1962 {ISD::SMIN, MVT::v4i32, 2}, in getMinMaxReductionCost()
1964 if (const auto *Entry = CostTableLookup(CostTblAdd, ISD::SMIN, LT.second)) in getMinMaxReductionCost()
H A DARMISelLowering.cpp225 for (auto Opcode : {ISD::ABS, ISD::ABDS, ISD::ABDU, ISD::SMIN, ISD::SMAX, in addTypeForNEON()
275 setOperationAction(ISD::SMIN, VT, Legal); in addMVEVectorTypes()
1038 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in ARMTargetLowering()
1605 setTargetDAGCombine({ISD::SMIN, ISD::SMAX}); in ARMTargetLowering()
4305 ? ISD::SMIN : ISD::SMAX; in LowerINTRINSIC_WO_CHAIN()
6038 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT, in LowerFP_TO_INT_SAT()
13394 if (N->getOpcode() == ISD::SMIN) { in PerformVQDMULHCombine()
18021 (Op0.getOpcode() != ISD::SMIN && Op0.getOpcode() != ISD::SMAX) || in PerformMinMaxToSatCombine()
18035 if (Min.getOpcode() != ISD::SMIN || Max.getOpcode() != ISD::SMAX || in PerformMinMaxToSatCombine()
18071 if (Min->getOpcode() != ISD::SMIN) in PerformMinMaxCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2138 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
2146 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
2154 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
2162 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
H A DAArch64ISelLowering.cpp681 setOperationAction(ISD::SMIN, MVT::i32, Legal); in AArch64TargetLowering()
682 setOperationAction(ISD::SMIN, MVT::i64, Legal); in AArch64TargetLowering()
1313 setOperationAction(ISD::SMIN, VT, Custom); in AArch64TargetLowering()
1543 setOperationAction(ISD::SMIN, VT, Custom); in AArch64TargetLowering()
1849 setOperationAction(ISD::SMIN, MVT::v1i64, Custom); in AArch64TargetLowering()
1850 setOperationAction(ISD::SMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
2073 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2332 setOperationAction(ISD::SMIN, VT, Default); in addTypeForFixedLengthSVE()
4710 SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
4711 SDValue Min2 = SrcVal2 ? DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt2, MinC) : SDValue(); in LowerVectorFP_TO_INT_SAT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp123 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp430 case ISD::SMIN: in getInverseMinMaxOpcode()
433 return ISD::SMIN; in getInverseMinMaxOpcode()
471 return ISD::SMIN; in getVecReduceBaseOpcode()
4322 case ISD::SMIN: in computeKnownBits()
4329 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in computeKnownBits()
4674 if (Val.getOpcode() == ISD::SMIN || Val.getOpcode() == ISD::SMAX || in isKnownToBeAPowerOfTwo()
4945 case ISD::SMIN: in ComputeNumSignBits()
4952 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in ComputeNumSignBits()
5547 case ISD::SMIN: in canCreateUndefOrPoison()
5974 case ISD::SMIN: { in isKnownNeverZero()
[all …]
H A DSelectionDAGDumper.cpp321 case ISD::SMIN: return "smin"; in getOperationName()
H A DLegalizeIntegerTypes.cpp106 case ISD::SMIN: in PromoteIntegerResult()
1163 Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax); in PromoteIntRes_ADDSUBSHLSAT()
1223 V = DAG.getNode(ISD::SMIN, dl, VT, V, in SaturateWidenedDIVFIX()
3053 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break; in ExpandIntegerResult()
3431 case ISD::SMIN: in getExpandedMinMaxOps()
3479 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(RHS))) { in ExpandIntRes_MINMAX()
3488 if (N->getOpcode() == ISD::SMIN) { in ExpandIntRes_MINMAX()
3543 case ISD::SMIN: in ExpandIntRes_MINMAX()
H A DLegalizeVectorOps.cpp449 case ISD::SMIN: in LegalizeOp()
1150 case ISD::SMIN: in Expand()
H A DLegalizeDAG.cpp2482 SDValue ClampN_Big = DAG.getNode(ISD::SMIN, dl, ExpVT, N, ClampMaxVal); in expandLdexp()
3736 case ISD::SMIN: in ExpandNode()
3745 case ISD::SMIN: Pred = ISD::SETLT; break; in ExpandNode()
5443 case ISD::SMIN: in PromoteNode()
5463 case ISD::SMIN: in PromoteNode()
H A DDAGCombiner.cpp1936 case ISD::SMIN: in visit()
5907 return CC == ISD::SETLT ? ISD::SMIN : (CC == ISD::SETGT ? ISD::SMAX : 0); in isSaturatingMinMax()
5938 case ISD::SMIN: in isSaturatingMinMax()
5942 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
5969 ConstantSDNode *MinCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N1 : N01); in isSaturatingMinMax()
5970 ConstantSDNode *MaxCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N01 : N1); in isSaturatingMinMax()
6089 case ISD::SMIN: AltOpcode = ISD::UMIN; break; in visitIMINMAX()
6091 case ISD::UMIN: AltOpcode = ISD::SMIN; break; in visitIMINMAX()
6099 if (Opcode == ISD::SMIN || Opcode == ISD::SMAX) in visitIMINMAX()
6101 N0, N1, N0, N1, Opcode == ISD::SMIN ? ISD::SETLT : ISD::SETGT, DAG)) in visitIMINMAX()
[all …]
H A DTargetLowering.cpp2308 case ISD::SMIN: in SimplifyDemandedBits()
2318 (Opc == ISD::SMIN || Opc == ISD::UMAX) ? ISD::OR : ISD::AND; in SimplifyDemandedBits()
2330 case ISD::SMIN: in SimplifyDemandedBits()
9671 isOperationLegal(ISD::SMIN, VT)) { in expandABS()
9674 return DAG.getNode(ISD::SMIN, dl, VT, Op, in expandABS()
9710 unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN; in expandABD()
10806 case ISD::SMIN: in expandIntMINMAX()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp568 setOperationAction({ISD::Constant, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
801 ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in SITargetLowering()
821 ISD::MUL, ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
966 ISD::SMIN, in SITargetLowering()
972 ISD::SMIN, in SITargetLowering()
6195 case ISD::SMIN: in LowerOperation()
7178 SDValue Clamp = DAG.getNode(ISD::SMIN, DL, ExpVT, ClampMin, MaxExp); in lowerFLDEXP()
7193 case ISD::SMIN: in getExtOpcodeForPromotedOp()
7226 Opc == ISD::SETCC || Opc == ISD::SELECT || Opc == ISD::SMIN || in promoteUniformOpToI32()
13811 case ISD::SMIN: in minMaxOpcToMin3Max3Opc()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp217 setOperationAction(ISD::SMIN, T, Legal); in initializeHVXLowering()
324 setOperationAction(ISD::SMIN, T, Custom); in initializeHVXLowering()
2841 SDValue Rsh01 = DAG.getNode(ISD::SMIN, dl, ResTy, {Rsh00, MW}); in ExpandHvxFpToInt()
3218 case ISD::SMIN: in LowerHvxOperation()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def186 VP_PROPERTY_FUNCTIONAL_SDOPC(SMIN)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp572 case ISD::SMIN: in NVPTXTargetLowering()
647 ISD::SMIN, ISD::SMULO, ISD::SMUL_LOHI, ISD::SRA, in NVPTXTargetLowering()
788 setOperationAction({ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, in NVPTXTargetLowering()
797 setI16x2OperationAction(ISD::SMIN, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2944 case ISD::SMIN: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp382 setOperationAction(ISD::SMIN, Ty, Legal); in addMSAIntType()
2072 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2084 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp401 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, in RISCVTargetLowering()
877 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, in RISCVTargetLowering()
1359 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
1635 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
6996 OP_CASE(SMIN) in getRISCVVLOp()
7019 VP_CASE(SMIN) // VP_SMIN in getRISCVVLOp()
8148 case ISD::SMIN: in LowerOperation()
8168 unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN; in LowerOperation()
11262 case ISD::SMIN: in lowerVECREDUCE()
14815 case ISD::SMIN: in getVecReduceOpcode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp207 setOperationAction(ISD::SMIN, IntVT, Legal); in initSPUActions()
2891 case ISD::SMIN: in isI32Insn()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp179 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp797 ISD::FMAD, ISD::SMIN, in initActions()

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