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Searched refs:SMIN (Results 1 – 25 of 38) sorted by relevance

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/freebsd/usr.bin/calendar/
H A Dsunpos.c188 #define SMIN(s) (((s) % 3600) / 60) macro
244 SHOUR(dial), SMIN(dial), SSEC(dial), in fequinoxsolstice()
283 SHOUR(dial), SMIN(dial), SSEC(dial), in fequinoxsolstice()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3597 { ISD::SMIN, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3598 { ISD::SMIN, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3663 { ISD::SMIN, MVT::v8i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3664 { ISD::SMIN, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3665 { ISD::SMIN, MVT::v32i16, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3666 { ISD::SMIN, MVT::v64i8, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3667 { ISD::SMIN, MVT::v4i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3668 { ISD::SMIN, MVT::v2i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3807 { ISD::SMIN, MVT::v2i64, { 2, 7, 2, 3 } }, in getIntrinsicInstrCost()
3808 { ISD::SMIN, MVT::v4i64, { 2, 7, 2, 3 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h696 SMIN, enumerator
H A DSDPatternMatch.h574 return BinaryOpc_match<LHS, RHS, true>(ISD::SMIN, L, R);
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1877 {ISD::SMIN, MVT::v16i8, 4}, in getMinMaxReductionCost()
1878 {ISD::SMIN, MVT::v8i16, 3}, in getMinMaxReductionCost()
1879 {ISD::SMIN, MVT::v4i32, 2}, in getMinMaxReductionCost()
1881 if (const auto *Entry = CostTableLookup(CostTblAdd, ISD::SMIN, LT.second)) in getMinMaxReductionCost()
H A DARMISelLowering.cpp220 for (auto Opcode : {ISD::ABS, ISD::ABDS, ISD::ABDU, ISD::SMIN, ISD::SMAX, in addTypeForNEON()
270 setOperationAction(ISD::SMIN, VT, Legal); in addMVEVectorTypes()
1040 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in ARMTargetLowering()
1612 setTargetDAGCombine({ISD::SMIN, ISD::SMAX}); in ARMTargetLowering()
4235 ? ISD::SMIN : ISD::SMAX; in LowerINTRINSIC_WO_CHAIN()
5965 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT, in LowerFP_TO_INT_SAT()
13327 if (N->getOpcode() == ISD::SMIN) { in PerformVQDMULHCombine()
17943 (Op0.getOpcode() != ISD::SMIN && Op0.getOpcode() != ISD::SMAX) || in PerformMinMaxToSatCombine()
17957 if (Min.getOpcode() != ISD::SMIN || Max.getOpcode() != ISD::SMAX || in PerformMinMaxToSatCombine()
17993 if (Min->getOpcode() != ISD::SMIN) in PerformMinMaxCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp103 case ISD::SMIN: in PromoteIntegerResult()
1118 Result = matcher.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax); in PromoteIntRes_ADDSUBSHLSAT()
1178 V = DAG.getNode(ISD::SMIN, dl, VT, V, in SaturateWidenedDIVFIX()
2870 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break; in ExpandIntegerResult()
3248 case ISD::SMIN: in getExpandedMinMaxOps()
3282 (N->getOpcode() == ISD::SMIN && isAllOnesConstant(RHS))) { in ExpandIntRes_MINMAX()
3291 if (N->getOpcode() == ISD::SMIN) { in ExpandIntRes_MINMAX()
3346 case ISD::SMIN: in ExpandIntRes_MINMAX()
H A DSelectionDAGDumper.cpp304 case ISD::SMIN: return "smin"; in getOperationName()
H A DLegalizeVectorOps.cpp435 case ISD::SMIN: in LegalizeOp()
1019 case ISD::SMIN: in Expand()
H A DSelectionDAG.cpp459 return ISD::SMIN; in getVecReduceBaseOpcode()
4085 case ISD::SMIN: in computeKnownBits()
4092 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in computeKnownBits()
4403 if (Val.getOpcode() == ISD::SMIN || Val.getOpcode() == ISD::SMAX || in isKnownToBeAPowerOfTwo()
4674 case ISD::SMIN: in ComputeNumSignBits()
4681 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in ComputeNumSignBits()
5263 case ISD::SMIN: in canCreateUndefOrPoison()
5577 case ISD::SMIN: { in isKnownNeverZero()
6266 case ISD::SMIN: return C1.sle(C2) ? C1 : C2; in FoldValue()
7018 case ISD::SMIN: in getNode()
[all …]
H A DLegalizeDAG.cpp2455 SDValue ClampN_Big = DAG.getNode(ISD::SMIN, dl, ExpVT, N, ClampMaxVal); in expandLdexp()
3613 case ISD::SMIN: in ExpandNode()
3622 case ISD::SMIN: Pred = ISD::SETLT; break; in ExpandNode()
5232 case ISD::SMIN: in PromoteNode()
5252 case ISD::SMIN: in PromoteNode()
H A DTargetLowering.cpp2240 case ISD::SMIN: in SimplifyDemandedBits()
2250 (Opc == ISD::SMIN || Opc == ISD::UMAX) ? ISD::OR : ISD::AND; in SimplifyDemandedBits()
2262 case ISD::SMIN: in SimplifyDemandedBits()
9228 isOperationLegal(ISD::SMIN, VT)) { in expandABS()
9231 return DAG.getNode(ISD::SMIN, dl, VT, Op, in expandABS()
9267 unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN; in expandABD()
10314 case ISD::SMIN: in expandIntMINMAX()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2138 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
2146 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
2154 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
2162 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
H A DAArch64ISelLowering.cpp667 setOperationAction(ISD::SMIN, MVT::i32, Legal); in AArch64TargetLowering()
668 setOperationAction(ISD::SMIN, MVT::i64, Legal); in AArch64TargetLowering()
1261 setOperationAction(ISD::SMIN, VT, Custom); in AArch64TargetLowering()
1451 setOperationAction(ISD::SMIN, VT, Custom); in AArch64TargetLowering()
1720 setOperationAction(ISD::SMIN, MVT::v1i64, Custom); in AArch64TargetLowering()
1721 setOperationAction(ISD::SMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
1904 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2095 setOperationAction(ISD::SMIN, VT, Default); in addTypeForFixedLengthSVE()
4552 SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
4609 SDValue Min = DAG.getNode(ISD::SMIN, DL, DstVT, NativeCvt, MinC); in LowerFP_TO_INT_SAT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp122 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp378 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, in RISCVTargetLowering()
381 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, in RISCVTargetLowering()
829 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, in RISCVTargetLowering()
1240 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
1455 setOperationAction(ISD::SMIN, XLenVT, Legal); in RISCVTargetLowering()
1480 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
5702 Result = DAG.getNode(ISD::SMIN, DL, MVT::i64, Result, SatMax); in lowerSADDSAT_SSUBSAT()
5990 OP_CASE(SMIN) in getRISCVVLOp()
6013 VP_CASE(SMIN) // VP_SMIN in getRISCVVLOp()
7031 case ISD::SMIN in LowerOperation()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp213 setOperationAction(ISD::SMIN, T, Legal); in initializeHVXLowering()
318 setOperationAction(ISD::SMIN, T, Custom); in initializeHVXLowering()
2804 SDValue Rsh01 = DAG.getNode(ISD::SMIN, dl, ResTy, {Rsh00, MW}); in ExpandHvxFpToInt()
3181 case ISD::SMIN: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1560 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
1732 setOperationAction(ISD::SMIN, VT, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def214 VP_PROPERTY_FUNCTIONAL_SDOPC(SMIN)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp470 case ISD::SMIN: in NVPTXTargetLowering()
536 ISD::SMIN, ISD::SMULO, ISD::SMUL_LOHI, ISD::SRA, in NVPTXTargetLowering()
677 setOperationAction(ISD::SMIN, Ty, Legal); in NVPTXTargetLowering()
687 setI16x2OperationAction(ISD::SMIN, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2803 case ISD::SMIN: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp552 setOperationAction({ISD::Constant, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
775 ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in SITargetLowering()
794 ISD::MUL, ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
906 ISD::SMIN, in SITargetLowering()
5848 case ISD::SMIN: in LowerOperation()
6733 SDValue Clamp = DAG.getNode(ISD::SMIN, DL, ExpVT, ClampMin, MaxExp); in lowerFLDEXP()
13037 case ISD::SMIN: in minMaxOpcToMin3Max3Opc()
13163 case ISD::SMIN: in supportsMin3Max3()
13215 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) { in performMinMaxCombine()
13220 if (Opc == ISD::SMAX && Op0.getOpcode() == ISD::SMIN && Op0.hasOneUse()) { in performMinMaxCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp343 setOperationAction(ISD::SMIN, Ty, Legal); in addMSAIntType()
2028 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2040 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp259 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
306 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
3847 return DAG.getNode(ISD::SMIN, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
3867 return DAG.getNode(ISD::SMIN, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp207 setOperationAction(ISD::SMIN, IntVT, Legal); in initSPUActions()
2907 case ISD::SMIN: in isI32Insn()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp716 ISD::FMAD, ISD::SMIN, in initActions()

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