Lines Matching refs:SMIN
667 setOperationAction(ISD::SMIN, MVT::i32, Legal); in AArch64TargetLowering()
668 setOperationAction(ISD::SMIN, MVT::i64, Legal); in AArch64TargetLowering()
1261 setOperationAction(ISD::SMIN, VT, Custom); in AArch64TargetLowering()
1451 setOperationAction(ISD::SMIN, VT, Custom); in AArch64TargetLowering()
1720 setOperationAction(ISD::SMIN, MVT::v1i64, Custom); in AArch64TargetLowering()
1721 setOperationAction(ISD::SMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
1904 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2095 setOperationAction(ISD::SMIN, VT, Default); in addTypeForFixedLengthSVE()
4552 SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
4609 SDValue Min = DAG.getNode(ISD::SMIN, DL, DstVT, NativeCvt, MinC); in LowerFP_TO_INT_SAT()
5705 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
6875 case ISD::SMIN: in LowerOperation()
10161 case ISD::SMIN: in LowerMinMax()
10180 case ISD::SMIN: in LowerMinMax()
26214 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV); in ReplaceNodeResults()