Lines Matching refs:SMIN
220 for (auto Opcode : {ISD::ABS, ISD::ABDS, ISD::ABDU, ISD::SMIN, ISD::SMAX, in addTypeForNEON()
270 setOperationAction(ISD::SMIN, VT, Legal); in addMVEVectorTypes()
1040 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in ARMTargetLowering()
1612 setTargetDAGCombine({ISD::SMIN, ISD::SMAX}); in ARMTargetLowering()
4235 ? ISD::SMIN : ISD::SMAX; in LowerINTRINSIC_WO_CHAIN()
5965 SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT, in LowerFP_TO_INT_SAT()
13327 if (N->getOpcode() == ISD::SMIN) { in PerformVQDMULHCombine()
17943 (Op0.getOpcode() != ISD::SMIN && Op0.getOpcode() != ISD::SMAX) || in PerformMinMaxToSatCombine()
17957 if (Min.getOpcode() != ISD::SMIN || Max.getOpcode() != ISD::SMAX || in PerformMinMaxToSatCombine()
17993 if (Min->getOpcode() != ISD::SMIN) in PerformMinMaxCombine()
17995 if (Min->getOpcode() != ISD::SMIN || Max->getOpcode() != ISD::SMAX) in PerformMinMaxCombine()
18935 case ISD::SMIN: in PerformDAGCombine()