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Searched refs:Regs (Results 1 – 25 of 95) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp132 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs, in getFrameHelperName() argument
150 for (auto Reg : Regs) { in getFrameHelperName()
314 SmallVectorImpl<unsigned> &Regs, in getOrCreateFrameHelper() argument
317 assert(Regs.size() >= 2); in getOrCreateFrameHelper()
318 auto Name = getFrameHelperName(Regs, Type, FpOffset); in getOrCreateFrameHelper()
328 int Size = (int)Regs.size(); in getOrCreateFrameHelper()
333 auto LRIdx = std::distance(Regs.begin(), llvm::find(Regs, AArch64::LR)); in getOrCreateFrameHelper()
338 assert(Regs[Size - 2] != AArch64::LR); in getOrCreateFrameHelper()
339 emitStore(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], in getOrCreateFrameHelper()
346 if (Regs[I - 1] == AArch64::LR) in getOrCreateFrameHelper()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h314 /// in the set, or Regs.size() if they are all allocated.
315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
316 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
317 if (!isAllocated(Regs[i])) in getFirstUnallocated()
319 return Regs.size(); in getFirstUnallocated()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
350 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
351 if (FirstUnalloc == Regs.size()) in AllocateReg()
355 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigne argument
390 AllocateReg(ArrayRef<MCPhysReg> Regs,const MCPhysReg * ShadowRegs) AllocateReg() argument
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H A DRegisterPressure.h276 RegSet Regs; variable
298 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
299 if (I == Regs.end()) in contains()
308 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
321 RegSet::iterator I = Regs.find(SparseIndex); in erase()
322 if (I == Regs.end()) in erase()
330 return Regs.size(); in size()
335 for (const IndexMaskPair &P : Regs) { in appendTo()
412 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
H A DMachineOutliner.h166 /// in \p Regs. in isAnyUnavailableAcrossOrOutOfSeq()
167 bool isAnyUnavailableAcrossOrOutOfSeq(std::initializer_list<Register> Regs, in isAnyUnavailableAcrossOrOutOfSeq()
171 return any_of(Regs, [&](Register Reg) { in isAnyUnavailableAcrossOrOutOfSeq()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp35 SmallVector<Register, 1> Regs; member in __anon9afe8d680111::GISelAsmOperandInfo
132 OpInfo.Regs.push_back(R); in getRegistersForValue()
346 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
357 OpInfo.Regs.size()); in lowerInlineAsm()
358 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
363 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front()); in lowerInlineAsm()
369 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
492 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
499 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm()
512 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
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H A DCallLowering.cpp187 Info.OrigRet.Regs[0] = ReturnHintAlignReg; in lowerCall()
303 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), in splitToValueTypes()
310 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); in splitToValueTypes()
316 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex, in splitToValueTypes()
374 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, in buildCopyFromRegs() argument
381 assert(OrigRegs[0] == Regs[0]); in buildCopyFromRegs()
386 Regs.size() == 1) { in buildCopyFromRegs()
387 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs()
397 OrigRegs.size() == 1 && Regs.size() == 1) { in buildCopyFromRegs()
398 Register SrcReg = Regs[0]; in buildCopyFromRegs()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp88 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
91 const std::deque<CodeGenRegister> &Regs,
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
381 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
387 for (auto &RE : Regs) { in EmitRegMappingTables()
403 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
448 for (auto &RE : Regs) { in EmitRegMappingTables()
508 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
512 for (auto &RE : Regs) { in EmitRegMapping()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h63 SmallVector<Register, 4> Regs; member
81 ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
84 : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()), in BaseArgInfo()
86 if (!Regs.empty() && Flags.empty()) in BaseArgInfo()
90 (Regs.empty() || Regs[0] == 0)) && in BaseArgInfo()
94 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue, unsigned OrigIndex,
97 : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed, &OrigValue) {}
298 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA); in assignValueToAddress()
H A DIRTranslator.h708 auto Regs = getOrCreateVRegs(Val); in getOrCreateVReg() local
709 if (Regs.empty()) in getOrCreateVReg()
711 assert(Regs.size() == 1 && in getOrCreateVReg()
713 return Regs[0]; in getOrCreateVReg()
718 auto &Regs = *VMap.getVRegs(Token); in getOrCreateConvergenceTokenVReg() local
719 if (!Regs.empty()) { in getOrCreateConvergenceTokenVReg()
720 assert(Regs.size() == 1 && in getOrCreateConvergenceTokenVReg()
722 return Regs[0]; in getOrCreateConvergenceTokenVReg()
726 Regs.push_back(Reg); in getOrCreateConvergenceTokenVReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp922 auto *Regs = in isXPLeafCandidate() local
940 if (MRI.isPhysRegModified(Regs->getStackPointerRegister())) in isXPLeafCandidate()
944 if (MRI.isPhysRegModified(Regs->getAddressOfCalleeRegister())) in isXPLeafCandidate()
949 if (MRI.isPhysRegModified(Regs->getReturnFunctionAddressRegister())) in isXPLeafCandidate()
971 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in assignCalleeSavedSpillSlots() local
988 CSI.push_back(CalleeSavedInfo(Regs.getAddressOfCalleeRegister())); in assignCalleeSavedSpillSlots()
992 CSI.push_back(CalleeSavedInfo(Regs.getReturnFunctionAddressRegister())); in assignCalleeSavedSpillSlots()
997 CSI.push_back(CalleeSavedInfo(Regs.getStackPointerRegister())); in assignCalleeSavedSpillSlots()
1002 CSI.push_back(CalleeSavedInfo(Regs.getADARegister())); in assignCalleeSavedSpillSlots()
1074 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in determineCalleeSaves() local
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H A DSystemZRegisterInfo.cpp243 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
245 return Regs->getCalleeSavedRegs(MF); in getCalleeSavedRegs()
253 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
254 return Regs->getCallPreservedMask(MF, CC); in getCallPreservedMask()
262 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
265 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true); in getReservedRegs()
270 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true); in getReservedRegs()
435 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in shouldCoalesce()
437 return TFI->hasFP(MF) ? Regs->getFramePointerRegister() in shouldCoalesce()
438 : Regs in shouldCoalesce()
453 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); getFrameRegister() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.cpp110 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
111 while (Regs) { in EmitVFPRegSave()
113 auto RangeMSB = llvm::bit_width(Regs); in EmitVFPRegSave()
114 auto RangeLen = llvm::countl_one(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
124 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DHWEventListener.h78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
81 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
101 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp872 const unsigned *Regs; in parseRegister() local
874 case GR32Reg: Regs = SystemZMC::GR32Regs; break; in parseRegister()
875 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break; in parseRegister()
876 case GR64Reg: Regs = SystemZMC::GR64Regs; break; in parseRegister()
877 case GR128Reg: Regs = SystemZMC::GR128Regs; break; in parseRegister()
878 case FP32Reg: Regs = SystemZMC::FP32Regs; break; in parseRegister()
879 case FP64Reg: Regs = SystemZMC::FP64Regs; break; in parseRegister()
880 case FP128Reg: Regs = SystemZMC::FP128Regs; break; in parseRegister()
881 case VR32Reg: Regs = SystemZMC::VR32Regs; break; in parseRegister()
882 case VR64Reg: Regs = SystemZMC::VR64Regs; break; in parseRegister()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1904 MutableArrayRef<std::pair<Register, int>> Regs, in insertMultibyteShift() argument
1929 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset; in insertMultibyteShift()
1931 Regs.slice(ShiftRegsOffset, ShiftRegsSize); in insertMultibyteShift()
1951 for (size_t I = 0; I < Regs.size(); I++) { in insertMultibyteShift()
1954 Regs[I] = ShiftRegs[ShiftRegsIdx]; in insertMultibyteShift()
1956 Regs[I] = std::pair(LowByte, 0); in insertMultibyteShift()
1958 Regs[I] = std::pair(ZeroReg, 0); in insertMultibyteShift()
1969 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8); in insertMultibyteShift()
1971 Regs.slice(0, ShiftRegsSize); in insertMultibyteShift()
2011 for (int I = Regs.size() - 1; I >= 0; I--) { in insertMultibyteShift()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVCallLowering.cpp492 if (Info.OrigRet.Regs.size() > 1) in lowerCall()
521 Info.OrigRet.Regs.empty() ? Register(0) : Info.OrigRet.Regs[0]; in lowerCall()
534 assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs"); in lowerCall()
535 ArgVRegs.push_back(Arg.Regs[0]); in lowerCall()
537 if (!GR->getSPIRVTypeForVReg(Arg.Regs[0])) in lowerCall()
538 GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MF); in lowerCall()
586 assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs"); in lowerCall()
588 IndirectCall.ArgRegs.push_back(Arg.Regs[0]); in lowerCall()
610 if (Arg.Regs.size() > 1) in lowerCall()
612 MIB.addUse(Arg.Regs[0]); in lowerCall()
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DTaint.cpp140 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
142 Regs = F.add(Regs, SubRegion, Kind); in addPartialTaint()
143 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs); in addPartialTaint()
290 if (const TaintedSubRegions *Regs = in getTaintedSymbolsImpl() local
293 for (auto I : *Regs) { in getTaintedSymbolsImpl()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp215 RegUnitIterator(const CodeGenRegister::Vec &Regs) in RegUnitIterator() argument
216 : RegI(Regs.begin()), RegE(Regs.end()) { in RegUnitIterator()
1200 std::vector<Record *> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1201 if (!Regs.empty() && Regs[0]->isSubClassOf("X86Reg")) { in CodeGenRegBank()
1212 Regs.insert(Regs.end(), TupRegs.begin(), TupRegs.end()); in CodeGenRegBank()
1215 llvm::sort(Regs, LessRecordRegister()); in CodeGenRegBank()
1217 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in CodeGenRegBank()
1218 getReg(Regs[i]); in CodeGenRegBank()
1220 llvm::sort(Regs, LessRecordRegister()); in CodeGenRegBank()
1222 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in CodeGenRegBank()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp329 SmallVector<int, 4> Regs; in visitSoftInstr() local
341 auto I = partition_point(Regs, [&](int I) { in visitSoftInstr()
344 Regs.insert(I, rx); in visitSoftInstr()
350 while (!Regs.empty()) { in visitSoftInstr()
352 dv = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
H A DAggressiveAntiDepBreaker.cpp80 std::vector<unsigned> &Regs, in GetGroupRegs() argument
85 Regs.push_back(Reg); in GetGroupRegs()
546 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
547 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
548 assert(!Regs.empty() && "Empty register group!"); in FindSuitableFreeRegisters()
549 if (Regs.empty()) in FindSuitableFreeRegisters()
557 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters()
576 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters()
637 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp182 Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end()); in assignCustomValue()
183 Arg.Regs = { CopyLo.getReg(0), CopyHi.getReg(0) }; in assignCustomValue()
270 MIRBuilder.buildUnmerge({LLT::scalar(32), LLT::scalar(32)}, Arg.Regs[0]); in assignCustomValue()
274 Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end()); in assignCustomValue()
275 Arg.Regs = { Lo, Hi }; in assignCustomValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp171 auto Regs = getRegisters(); in getRegister() local
172 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
173 if (It == Regs.end()) in getRegister()
772 auto Regs = getRegisters(); in toString() local
773 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { in toString()
774 if (I != Regs.begin()) in toString()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMachineFunctionInfo.h148 void setRVPushRegs(unsigned Regs) { RVPushRegs = Regs; }
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp318 Register ValVReg = Arg.Regs[RegIndex]; in assignValueToAddress()
450 if (CurVReg != CurArgInfo.Regs[0]) { in lowerReturn()
451 CurArgInfo.Regs[0] = CurVReg; in lowerReturn()
681 assert(OrigArg.Regs.size() == 1 && in lowerFormalArguments()
682 MRI.getType(OrigArg.Regs[0]).getSizeInBits() == 1 && in lowerFormalArguments()
688 Register OrigReg = OrigArg.Regs[0]; in lowerFormalArguments()
690 OrigArg.Regs[0] = WideReg; in lowerFormalArguments()
1288 assert(OutArg.Regs.size() == 1 && in lowerCall()
1289 MRI.getType(OutArg.Regs[0]).getSizeInBits() == 1 && in lowerCall()
1294 OutArg.Regs[0] = in lowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp180 ArrayRef<std::pair<unsigned, bool>> Regs,
186 ArrayRef<std::pair<unsigned, bool>> Regs,
617 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg() argument
619 for (const std::pair<unsigned, bool> &R : Regs) in ContainsReg()
632 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti() argument
634 unsigned NumRegs = Regs.size(); in CreateLoadStoreMulti()
648 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()
688 NewBase = Regs[NumRegs-1].first; in CreateLoadStoreMulti()
696 for (const std::pair<unsigned, bool> &R : Regs) in CreateLoadStoreMulti()
730 (!isi32Store(Opcode) || !ContainsReg(Regs, Base)); in CreateLoadStoreMulti()
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