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Searched refs:Regs (Results 1 – 25 of 97) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp126 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs, in getFrameHelperName() argument
144 for (auto Reg : Regs) { in getFrameHelperName()
304 SmallVectorImpl<unsigned> &Regs, in getOrCreateFrameHelper() argument
307 assert(Regs.size() >= 2); in getOrCreateFrameHelper()
308 auto Name = getFrameHelperName(Regs, Type, FpOffset); in getOrCreateFrameHelper()
318 int Size = (int)Regs.size(); in getOrCreateFrameHelper()
323 auto LRIdx = std::distance(Regs.begin(), llvm::find(Regs, AArch64::LR)); in getOrCreateFrameHelper()
328 assert(Regs[Size - 2] != AArch64::LR); in getOrCreateFrameHelper()
329 emitStore(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], in getOrCreateFrameHelper()
336 if (Regs[I - 1] == AArch64::LR) in getOrCreateFrameHelper()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h317 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
318 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
319 if (!isAllocated(Regs[i])) in getFirstUnallocated()
321 return Regs.size(); in getFirstUnallocated()
351 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
352 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
353 if (FirstUnalloc == Regs.size()) in AllocateReg()
357 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
365 ArrayRef<MCPhysReg> AllocateRegBlock(ArrayRef<MCPhysReg> Regs, in AllocateRegBlock() argument
367 if (RegsRequired > Regs.size()) in AllocateRegBlock()
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H A DRegisterPressure.h279 RegSet Regs; variable
301 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
302 if (I == Regs.end()) in contains()
311 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
324 RegSet::iterator I = Regs.find(SparseIndex); in erase()
325 if (I == Regs.end()) in erase()
333 return Regs.size(); in size()
337 for (const IndexMaskPair &P : Regs) { in appendTo()
414 LLVM_ABI void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp35 SmallVector<Register, 1> Regs; member in __anon9afe8d680111::GISelAsmOperandInfo
132 OpInfo.Regs.push_back(R); in getRegistersForValue()
346 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
357 OpInfo.Regs.size()); in lowerInlineAsm()
358 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
363 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front()); in lowerInlineAsm()
369 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
492 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
499 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm()
512 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
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H A DCallLowering.cpp186 Info.OrigRet.Regs[0] = ReturnHintAlignReg; in lowerCall()
302 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), in splitToValueTypes()
309 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); in splitToValueTypes()
315 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex, in splitToValueTypes()
373 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, in buildCopyFromRegs() argument
380 assert(OrigRegs[0] == Regs[0]); in buildCopyFromRegs()
385 Regs.size() == 1) { in buildCopyFromRegs()
386 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs()
396 OrigRegs.size() == 1 && Regs.size() == 1) { in buildCopyFromRegs()
397 Register SrcReg = Regs[0]; in buildCopyFromRegs()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp88 void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs,
91 const std::deque<CodeGenRegister> &Regs,
212 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
214 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
375 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
381 for (auto &RE : Regs) { in EmitRegMappingTables()
397 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
442 for (auto &RE : Regs) { in EmitRegMappingTables()
502 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
506 for (auto &RE : Regs) { in EmitRegMapping()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp954 auto *Regs = in isXPLeafCandidate() local
972 if (MRI.isPhysRegModified(Regs->getStackPointerRegister())) in isXPLeafCandidate()
976 if (MRI.isPhysRegModified(Regs->getAddressOfCalleeRegister())) in isXPLeafCandidate()
981 if (MRI.isPhysRegModified(Regs->getReturnFunctionAddressRegister())) in isXPLeafCandidate()
1003 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in assignCalleeSavedSpillSlots() local
1020 CSI.push_back(CalleeSavedInfo(Regs.getAddressOfCalleeRegister())); in assignCalleeSavedSpillSlots()
1024 CSI.push_back(CalleeSavedInfo(Regs.getReturnFunctionAddressRegister())); in assignCalleeSavedSpillSlots()
1029 CSI.push_back(CalleeSavedInfo(Regs.getStackPointerRegister())); in assignCalleeSavedSpillSlots()
1034 CSI.push_back(CalleeSavedInfo(Regs.getADARegister())); in assignCalleeSavedSpillSlots()
1106 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in determineCalleeSaves() local
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H A DSystemZRegisterInfo.cpp243 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
245 return Regs->getCalleeSavedRegs(MF); in getCalleeSavedRegs()
253 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
254 return Regs->getCallPreservedMask(MF, CC); in getCallPreservedMask()
266 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
269 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true); in getReservedRegs()
274 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true); in getReservedRegs()
439 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getFrameRegister() local
441 return TFI->hasFP(MF) ? Regs->getFramePointerRegister() in getFrameRegister()
442 : Regs->getStackPointerRegister(); in getFrameRegister()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h64 SmallVector<Register, 4> Regs; member
82 ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
85 : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs), OrigValue(OrigValue), in BaseArgInfo()
87 if (!Regs.empty() && Flags.empty()) in BaseArgInfo()
91 (Regs.empty() || Regs[0] == 0)) && in BaseArgInfo()
95 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue, unsigned OrigIndex,
98 : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed, &OrigValue) {}
299 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA); in assignValueToAddress()
H A DIRTranslator.h705 auto Regs = getOrCreateVRegs(Val); in getOrCreateVReg() local
706 if (Regs.empty()) in getOrCreateVReg()
708 assert(Regs.size() == 1 && in getOrCreateVReg()
710 return Regs[0]; in getOrCreateVReg()
715 auto &Regs = *VMap.getVRegs(Token); in getOrCreateConvergenceTokenVReg() local
716 if (!Regs.empty()) { in getOrCreateConvergenceTokenVReg()
717 assert(Regs.size() == 1 && in getOrCreateConvergenceTokenVReg()
719 return Regs[0]; in getOrCreateConvergenceTokenVReg()
723 Regs.push_back(Reg); in getOrCreateConvergenceTokenVReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.cpp110 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
111 while (Regs) { in EmitVFPRegSave()
113 auto RangeMSB = llvm::bit_width(Regs); in EmitVFPRegSave()
114 auto RangeLen = llvm::countl_one(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
124 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DHWEventListener.h79 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
82 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
100 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
102 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp898 const unsigned *Regs; in parseRegister() local
900 case GR32Reg: Regs = SystemZMC::GR32Regs; break; in parseRegister()
901 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break; in parseRegister()
902 case GR64Reg: Regs = SystemZMC::GR64Regs; break; in parseRegister()
903 case GR128Reg: Regs = SystemZMC::GR128Regs; break; in parseRegister()
904 case FP16Reg: Regs = SystemZMC::FP16Regs; break; in parseRegister()
905 case FP32Reg: Regs = SystemZMC::FP32Regs; break; in parseRegister()
906 case FP64Reg: Regs = SystemZMC::FP64Regs; break; in parseRegister()
907 case FP128Reg: Regs = SystemZMC::FP128Regs; break; in parseRegister()
908 case VR16Reg: Regs = SystemZMC::VR16Regs; break; in parseRegister()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1858 MutableArrayRef<std::pair<Register, int>> Regs, in insertMultibyteShift() argument
1883 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset; in insertMultibyteShift()
1885 Regs.slice(ShiftRegsOffset, ShiftRegsSize); in insertMultibyteShift()
1905 for (size_t I = 0; I < Regs.size(); I++) { in insertMultibyteShift()
1908 Regs[I] = ShiftRegs[ShiftRegsIdx]; in insertMultibyteShift()
1910 Regs[I] = std::pair(LowByte, 0); in insertMultibyteShift()
1912 Regs[I] = std::pair(ZeroReg, 0); in insertMultibyteShift()
1923 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8); in insertMultibyteShift()
1925 Regs.slice(0, ShiftRegsSize); in insertMultibyteShift()
1965 for (int I = Regs.size() - 1; I >= 0; I--) { in insertMultibyteShift()
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/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DTaint.cpp140 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
142 Regs = F.add(Regs, SubRegion, Kind); in addPartialTaint()
143 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs); in addPartialTaint()
298 if (const TaintedSubRegions *Regs = in getTaintedSymbolsImpl() local
301 for (auto I : *Regs) { in getTaintedSymbolsImpl()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp329 SmallVector<int, 4> Regs; in visitSoftInstr() local
341 auto I = partition_point(Regs, [&](int I) { in visitSoftInstr()
344 Regs.insert(I, rx); in visitSoftInstr()
350 while (!Regs.empty()) { in visitSoftInstr()
352 dv = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
H A DAggressiveAntiDepBreaker.cpp79 unsigned Group, std::vector<MCRegister> &Regs, in GetGroupRegs() argument
84 Regs.push_back(Reg); in GetGroupRegs()
550 std::vector<MCRegister> Regs; in FindSuitableFreeRegisters() local
551 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
552 assert(!Regs.empty() && "Empty register group!"); in FindSuitableFreeRegisters()
553 if (Regs.empty()) in FindSuitableFreeRegisters()
561 for (MCRegister Reg : Regs) { in FindSuitableFreeRegisters()
580 for (MCRegister Reg : Regs) { in FindSuitableFreeRegisters()
641 for (MCRegister Reg : Regs) { in FindSuitableFreeRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp273 auto &Regs = It->second.Regs; in addPreloadedKernArg() local
276 Regs.push_back(PreloadReg); in addPreloadedKernArg()
279 Regs.reserve(AllocSizeDWord); in addPreloadedKernArg()
281 Regs.push_back(getNextUserSGPR()); in addPreloadedKernArg()
288 return &Regs; in addPreloadedKernArg()
499 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR() local
522 SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin(); in allocateVGPRSpillToAGPR()
525 NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) { in allocateVGPRSpillToAGPR()
530 if (NextSpillReg == Regs.end()) { // Registers exhausted in allocateVGPRSpillToAGPR()
H A DAMDGPUCallLowering.cpp250 ? extendRegister(Arg.Regs[ValRegIndex], VA) in assignValueToAddress()
251 : Arg.Regs[ValRegIndex]; in assignValueToAddress()
324 assert(RetInfo.Regs.size() == 1 && "expect only simple return values"); in lowerReturnVal()
327 assert(RetInfo.Regs.size() == 1 && "expect only simple return values"); in lowerReturnVal()
340 if (Reg != RetInfo.Regs[0]) { in lowerReturnVal()
341 RetInfo.Regs[0] = Reg; in lowerReturnVal()
440 assert(SplitArg.Regs.size() == 1); in lowerParameter()
442 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
1247 assert(FallbackExecArg.Regs.size() == 1 && in lowerTailCall()
1273 MIB.addReg(Arg.Regs[0]); in lowerTailCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVCallLowering.cpp551 if (Info.OrigRet.Regs.size() > 1) in lowerCall()
580 Info.OrigRet.Regs.empty() ? Register(0) : Info.OrigRet.Regs[0]; in lowerCall()
606 assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs"); in lowerCall()
607 Register ArgReg = Arg.Regs[0]; in lowerCall()
698 assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs"); in lowerCall()
700 IndirectCall.ArgRegs.push_back(Arg.Regs[0]); in lowerCall()
723 if (Arg.Regs.size() > 1) in lowerCall()
725 MIB.addUse(Arg.Regs[0]); in lowerCall()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1146 std::vector<const Record *> Regs = RC.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1147 if (!Regs.empty() && Regs[0]->isSubClassOf("X86Reg")) { in CodeGenRegBank()
1156 llvm::append_range(Regs, TupRegs); in CodeGenRegBank()
1159 llvm::sort(Regs, LessRecordRegister()); in CodeGenRegBank()
1161 for (const Record *Reg : Regs) in CodeGenRegBank()
1164 llvm::sort(Regs, LessRecordRegister()); in CodeGenRegBank()
1166 for (const Record *Reg : Regs) in CodeGenRegBank()
1719 CodeGenRegister::Vec Regs; member
1748 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
1749 if (Regs.empty()) in computeUberSets()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp194 auto Regs = getRegisters(); in getRegister() local
195 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
196 if (It == Regs.end()) in getRegister()
809 auto Regs = getRegisters(); in toString() local
810 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { in toString()
811 if (I != Regs.begin()) in toString()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp182 Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end()); in assignCustomValue()
183 Arg.Regs = { CopyLo.getReg(0), CopyHi.getReg(0) }; in assignCustomValue()
270 MIRBuilder.buildUnmerge({LLT::scalar(32), LLT::scalar(32)}, Arg.Regs[0]); in assignCustomValue()
274 Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end()); in assignCustomValue()
275 Arg.Regs = { Lo, Hi }; in assignCustomValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp367 Register ValVReg = Arg.Regs[RegIndex]; in assignValueToAddress()
499 if (CurVReg != CurArgInfo.Regs[0]) { in lowerReturn()
500 CurArgInfo.Regs[0] = CurVReg; in lowerReturn()
730 assert(OrigArg.Regs.size() == 1 && in lowerFormalArguments()
731 MRI.getType(OrigArg.Regs[0]).getSizeInBits() == 1 && in lowerFormalArguments()
737 Register OrigReg = OrigArg.Regs[0]; in lowerFormalArguments()
739 OrigArg.Regs[0] = WideReg; in lowerFormalArguments()
1337 assert(OutArg.Regs.size() == 1 && in lowerCall()
1338 MRI.getType(OutArg.Regs[0]).getSizeInBits() == 1 && in lowerCall()
1343 OutArg.Regs[0] = in lowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp177 ArrayRef<std::pair<unsigned, bool>> Regs,
183 ArrayRef<std::pair<unsigned, bool>> Regs,
614 static bool ContainsReg(ArrayRef<std::pair<unsigned, bool>> Regs, in ContainsReg() argument
616 for (const std::pair<unsigned, bool> &R : Regs) in ContainsReg()
629 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti() argument
631 unsigned NumRegs = Regs.size(); in CreateLoadStoreMulti()
645 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()
685 NewBase = Regs[NumRegs-1].first; in CreateLoadStoreMulti()
693 for (const std::pair<unsigned, bool> &R : Regs) in CreateLoadStoreMulti()
727 (!isi32Store(Opcode) || !ContainsReg(Regs, Base)); in CreateLoadStoreMulti()
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