180         ArrayRef<std::pair<unsigned, bool>> Regs,
186         ArrayRef<std::pair<unsigned, bool>> Regs,
617 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,  in ContainsReg()  argument
619   for (const std::pair<unsigned, bool> &R : Regs)  in ContainsReg()
632     ArrayRef<std::pair<unsigned, bool>> Regs,  in CreateLoadStoreMulti()  argument
634   unsigned NumRegs = Regs.size();  in CreateLoadStoreMulti()
648   if (isThumb1 && ContainsReg(Regs, Base)) {  in CreateLoadStoreMulti()
688       NewBase = Regs[NumRegs-1].first;  in CreateLoadStoreMulti()
696         for (const std::pair<unsigned, bool> &R : Regs)  in CreateLoadStoreMulti()
730       (!isi32Store(Opcode) || !ContainsReg(Regs, Base));  in CreateLoadStoreMulti()
804       assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs");  in CreateLoadStoreMulti()
827   for (const std::pair<unsigned, bool> &R : Regs)  in CreateLoadStoreMulti()
839     ArrayRef<std::pair<unsigned, bool>> Regs,  in CreateLoadStoreDouble()  argument
845   assert(Regs.size() == 2);  in CreateLoadStoreDouble()
849     MIB.addReg(Regs[0].first, RegState::Define)  in CreateLoadStoreDouble()
850        .addReg(Regs[1].first, RegState::Define);  in CreateLoadStoreDouble()
852     MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))  in CreateLoadStoreDouble()
853        .addReg(Regs[1].first, getKillRegState(Regs[1].second));  in CreateLoadStoreDouble()
865   SmallVector<std::pair<unsigned, bool>, 8> Regs;  in MergeOpsUpdate()  local
876     Regs.push_back(std::make_pair(Reg, IsKill));  in MergeOpsUpdate()
914                                    Opcode, Pred, PredReg, DL, Regs,  in MergeOpsUpdate()
918                                   Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);  in MergeOpsUpdate()