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Searched refs:RegClass (Results 1 – 25 of 95) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td133 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
136 vti.LMul, vti.AVL, vti.RegClass,
149 vti.LMul, vti.AVL, vti.RegClass,
208 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
211 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
223 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
226 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
237 (fvti.Vector fvti.RegClass:$rs1))),
243 fvti.RegClass:$rs1,
253 (fvti.Vector fvti.RegClass:$rs1))),
[all …]
H A DRISCVInstrInfoVVLPatterns.td949 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
950 vti.RegClass, isSEWAware>;
953 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
966 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
980 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
981 vti.RegClass>;
984 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
1000 vti.LMul, wti.RegClass, vti.RegClass>;
1003 vti.Log2SEW, vti.LMul, wti.RegClass,
1004 vti.RegClass>;
[all …]
H A DRISCVInstrInfoZvk.td593 def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1))),
596 vti.RegClass:$rs1,
614 def : Pat<(vti.Vector (and (xor vti.RegClass:$rs1,
616 vti.RegClass:$rs2)),
619 vti.RegClass:$rs2,
620 vti.RegClass:$rs1,
624 vti.RegClass:$rs2)),
627 vti.RegClass:$rs2,
631 vti.RegClass:$rs2)),
634 vti.RegClass:$rs2,
[all …]
H A DRISCVInstrInfoVPseudos.td291 VReg RegClass = M.vrclass;
996 class VPseudoNullaryNoMask<VReg RegClass> :
997 Pseudo<(outs RegClass:$rd),
998 (ins RegClass:$passthru,
1010 class VPseudoNullaryMask<VReg RegClass> :
1011 Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
1012 (ins GetVRegNoV0<RegClass>.R:$passthru,
4574 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>;
4590 vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
4592 vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
[all …]
H A DRISCVInstrInfoXRivos.td102 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
103 vti.RegClass, isSEWAware>;
176 def : Pat<(XLenVT (ri_vextract (vti.Vector vti.RegClass:$vs2), uimm5:$imm)),
180 def : Pat<(vti.Vector (ri_vinsert_vl (vti.Vector vti.RegClass:$merge),
H A DRISCVInstrInfoXSf.td701 payload5, vti.RegClass, kind, op1_kind>;
705 vti.RegClass, kind, op1_kind>;
709 vti.RegClass, kind, op1_kind>;
718 wti.RegClass, vti.RegClass, kind, op1_kind>;
722 wti.RegClass, vti.RegClass, kind, op1_kind>;
726 wti.RegClass, vti.RegClass, kind, op1_kind>;
752 VdInfo.RegClass, VR, Vs2Info.RegClass>;
795 Vti.Log2SEW, Vti.RegClass,
796 Wti.RegClass, Wti.ScalarRegClass>;
806 defm : VPatVC_XV<"vv", "VV", vti, vti.Vector, vti.RegClass>;
[all …]
H A DRISCVInstrInfoXAndes.td516 fwti.RegClass, fvti.RegClass>;
528 fvti.RegClass, fwti.RegClass>;
567 vti.Log2SEW, vti.RegClass,
568 vti.RegClass, FPR32>;
589 wti.RegClass, vti.RegClass, vti.RegClass>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrCMovSetCC.td18 def rr#suffix : ITy<0x40, MRMSrcRegCC, t, (outs t.RegClass:$dst),
19 (ins t.RegClass:$src1, t.RegClass:$src2, ccode:$cond),
21 [(set t.RegClass:$dst, (X86cmov t.RegClass:$src1,
22 … t.RegClass:$src2, timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
24 def rm#suffix : ITy<0x40, MRMSrcMemCC, t, (outs t.RegClass:$dst),
25 (ins t.RegClass:$src1, t.MemOperand:$src2, ccode:$cond),
27 [(set t.RegClass:$dst, (X86cmov t.RegClass:$src1,
34 def rr : ITy<0x40, MRMDestRegCC, t, (outs t.RegClass:$dst),
35 (ins t.RegClass:$src1, ccode:$cond),
37 [(set t.RegClass:$dst,
[all …]
H A DX86InstrUtils.td145 /// RegClass - This is the register class associated with this type. For
147 RegisterClass RegClass = regclass;
975 : ITy<o, MRMDestReg, t, out, (ins t.RegClass:$src1, t.RegClass:$src2), m,
980 [(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,
990 (outs t.RegClass:$dst), []>, NDD<ndd>;
999 (outs t.RegClass:$dst),
1000 [(set t.RegClass:$dst, EFLAGS,
1001 (node t.RegClass:$src1, t.RegClass:$src2))]>, DefEFLAGS, NDD<ndd>;
1010 : BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
1011 [(set t.RegClass:$dst, EFLAGS,
[all …]
H A DX86InstrArithmetic.td278 (outs t.RegClass:$dst)> {
283 (outs t.RegClass:$dst), []> {
288 (outs t.RegClass:$dst),
289 [(set t.RegClass:$dst, EFLAGS, (X86smul_flag t.RegClass:$src1,
294 : BinOpMI8<"imul", binop_ndd_args, t, MRMSrcMem, (outs t.RegClass:$dst)> {
300 (outs t.RegClass:$dst), []> {
305 (outs t.RegClass:$dst),
306 [(set t.RegClass:$dst, EFLAGS, (X86smul_flag (t.LoadNode addr:$src1),
355 (outs t.RegClass:$dst)> {
360 (outs t.RegClass:$dst), []> {
[all …]
H A DX86InstrMisc.td1094 def rm#suffix : ITy<o, MRMSrcMem, t, (outs t.RegClass:$dst),
1096 [(set t.RegClass:$dst, (bswap (t.LoadNode addr:$src1)))]>,
1099 (ins t.MemOperand:$dst, t.RegClass:$src1),
1101 [(store (bswap t.RegClass:$src1), addr:$dst)]>,
1118 def rr : ITy<0x61, MRMDestReg, t, (outs t.RegClass:$dst),
1119 (ins t.RegClass:$src1), "movbe", unaryop_ndd_args,
1120 [(set t.RegClass:$dst, (bswap t.RegClass:$src1))]>,
1122 def rr_REV : ITy<0x60, MRMSrcReg, t, (outs t.RegClass:$dst),
1123 (ins t.RegClass:$src1), "movbe", unaryop_ndd_args, []>,
1164 def rr#suffix : ITy<o, MRMSrcReg, t, (outs t.RegClass:$dst),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/DWARFCFIChecker/
H A DRegisters.h33 for (auto &&RegClass : MCRI->regclasses()) in getSuperRegs()
34 for (unsigned I = 0; I < RegClass.getNumRegs(); I++) { in getSuperRegs()
35 MCPhysReg Reg = RegClass.getRegister(I); in getSuperRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp67 return MCDesc.operands()[0].RegClass >= 0 && in hasType()
68 MCDesc.operands()[1].RegClass >= 0 && in hasType()
69 MCDesc.operands()[0].RegClass != SPIRV::TYPERegClassID && in hasType()
70 MCDesc.operands()[1].RegClass == SPIRV::TYPERegClassID; in hasType()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
99 CopyLocalOpc = WebAssembly::getCopyOpcodeForRegClass(RegClass); in maybeRewriteToFallthrough()
100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
H A DWebAssemblyRegStackify.cpp108 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
109 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
112 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
115 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
120 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
125 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
670 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
671 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
672 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
682 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
82 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp37 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
38 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
40 RI.RegClass = nullptr; in PhysicalRegisterInfo()
43 RI.RegClass = RC; in PhysicalRegisterInfo()
173 RI.RegClass ? RI.RegClass->LaneMask : LaneBitmask::getAll(); in mapTo()
H A DRegisterClassInfo.cpp53 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
130 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp156 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
158 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
159 assert(RegClass->isAllocatable() && in createVirtualRegister()
164 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h312 using RegClass = Bitfield::Element<unsigned, 16, 14>; variable
318 unsigned getRegClass() const { return Bitfield::get<RegClass>(Storage); } in getRegClass()
408 Bitfield::set<RegClass>(Storage, RC + 1); in setRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPreloadKernArgProlog.cpp45 const TargetRegisterClass *RegClass; member
168 AMDGPU::sub0, Config.RegClass); in getLoadParameters()
H A DGCNDPPCombine.cpp198 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; in getOperandSize() local
199 if (RegClass == -1) in getOperandSize()
203 return TRI->getRegSizeInBits(*TRI->getRegClass(RegClass)); in getOperandSize()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBanks.td10 // as InstructionSelector RegClass checking code relies on them
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp139 bool validateRegister(const Record *Reg, const Record *RegClass);
159 const Record *RegClass) { in validateRegister() argument
161 assert(RegClass->isSubClassOf("RegisterClass") && in validateRegister()
163 const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass); in validateRegister()

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