Lines Matching refs:RegClass
264 (outs t.RegClass:$dst)> {
269 (outs t.RegClass:$dst), []> {
274 (outs t.RegClass:$dst),
275 [(set t.RegClass:$dst, EFLAGS, (X86smul_flag t.RegClass:$src1,
280 : BinOpMI8<"imul", binop_ndd_args, t, MRMSrcMem, (outs t.RegClass:$dst)> {
286 (outs t.RegClass:$dst), []> {
291 (outs t.RegClass:$dst),
292 [(set t.RegClass:$dst, EFLAGS, (X86smul_flag (t.LoadNode addr:$src1),
341 (outs t.RegClass:$dst)> {
346 (outs t.RegClass:$dst), []> {
350 : BinOpMI8<"imulzu", binop_ndd_args, t, MRMSrcMem, (outs t.RegClass:$dst)> {
356 (outs t.RegClass:$dst), []> {
379 let Pattern = [(set t.RegClass:$dst, EFLAGS,
380 (X86add_flag_nocf t.RegClass:$src1, 1))];
383 let Pattern = [(set t.RegClass:$dst, EFLAGS,
384 (X86sub_flag_nocf t.RegClass:$src1, 1))];
397 let Pattern = [(set t.RegClass:$dst, EFLAGS, (add (t.LoadNode addr:$src1), 1))];
400 let Pattern = [(set t.RegClass:$dst, EFLAGS, (add (t.LoadNode addr:$src1), -1))];
1357 [(set t.RegClass:$dst, EFLAGS, (node (not t.RegClass:$src1),
1358 t.RegClass:$src2))];
1360 [(set t.RegClass:$dst, EFLAGS, (node (not t.RegClass:$src1),
1362 def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst),
1363 (ins t.RegClass:$src1, t.RegClass:$src2), "andn",
1365 def rm#suffix : ITy<0xF2, MRMSrcMem, t, (outs t.RegClass:$dst),
1366 (ins t.RegClass:$src1, t.MemOperand:$src2), "andn",
1410 def rr : ITy<0xF6, MRMSrcReg, t, (outs t.RegClass:$dst1, t.RegClass:$dst2),
1411 (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD, VEX,
1414 def rm : ITy<0xF6, MRMSrcMem, t, (outs t.RegClass:$dst1, t.RegClass:$dst2),
1420 (outs t.RegClass:$dst1, t.RegClass:$dst2),
1421 (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD,
1425 (outs t.RegClass:$dst1, t.RegClass:$dst2),
1431 def Hrr : PseudoI<(outs t.RegClass:$dst), (ins t.RegClass:$src), []>,
1434 def Hrm : PseudoI<(outs t.RegClass:$dst), (ins t.MemOperand:$src), []>,