Lines Matching refs:RegClass
145 /// RegClass - This is the register class associated with this type. For
147 RegisterClass RegClass = regclass;
977 : ITy<o, MRMDestReg, t, out, (ins t.RegClass:$src1, t.RegClass:$src2), m,
982 [(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,
992 (outs t.RegClass:$dst), []>, NDD<ndd>;
1001 (outs t.RegClass:$dst),
1002 [(set t.RegClass:$dst, EFLAGS,
1003 (node t.RegClass:$src1, t.RegClass:$src2))]>, DefEFLAGS, NDD<ndd>;
1012 : BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
1013 [(set t.RegClass:$dst, EFLAGS,
1014 (node t.RegClass:$src1, t.RegClass:$src2,
1026 : ITy<o, MRMSrcMem, t, out, (ins t.RegClass:$src1, t.MemOperand:$src2), m,
1034 [(set EFLAGS, (node t.RegClass:$src1,
1038 : BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
1042 : BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
1043 [(set t.RegClass:$dst, EFLAGS, (node t.RegClass:$src1,
1048 : BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
1049 [(set t.RegClass:$dst, EFLAGS,
1050 (node t.RegClass:$src1, (t.LoadNode addr:$src2), EFLAGS))]>,
1061 : ITy<o, f, t, out, (ins t.RegClass:$src1, t.ImmOperand:$src2), m,
1069 [(set EFLAGS, (node t.RegClass:$src1,
1073 : BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),
1077 : ITy<0xC1, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2), m,
1079 [(set t.RegClass:$dst, (node t.RegClass:$src1, (i8 imm:$src2)))]>, NDD<ndd> {
1084 : BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),
1085 [(set t.RegClass:$dst, EFLAGS,
1086 (node t.RegClass:$src1, t.ImmOperator:$src2))]>, DefEFLAGS, NDD<ndd>;
1090 : BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),
1091 [(set t.RegClass:$dst, EFLAGS,
1092 (node t.RegClass:$src1, t.ImmOperator:$src2,
1098 : ITy<o, f, t, out, (ins t.RegClass:$src1, t.Imm8Operand:$src2), m,
1107 …: BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, NDD<…
1110 …: BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, DefE…
1114 …: BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, DefE…
1120 : ITy<o, MRMDestMem, t, out, (ins t.MemOperand:$src1, t.RegClass:$src2), m,
1127 : BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst), []>, NDD<1>;
1130 : BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst),
1131 [(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1),
1132 t.RegClass:$src2))]>, DefEFLAGS, NDD<1>;
1136 [(set EFLAGS, (node (t.LoadNode addr:$src1), t.RegClass:$src2))]>,
1150 [(store (node (load addr:$src1), t.RegClass:$src2), addr:$src1),
1162 : BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst),
1163 [(set t.RegClass:$dst, EFLAGS, (node (load addr:$src1),
1164 t.RegClass:$src2, EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<1>,
1170 [(store (node (load addr:$src1), t.RegClass:$src2, EFLAGS),
1197 : BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst), []>,
1202 : BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),
1203 [(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1), t.ImmOperator:$src2))]>,
1221 : BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),
1222 [(set t.RegClass:$dst, EFLAGS, (node (t.VT (load addr:$src1)),
1253 …: BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>, Sched<[WriteALU.Folded, WriteALU.Read…
1256 : BinOpMI8U<m, binop_ndd_args, t, f, (outs t.RegClass:$dst),
1257 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), (i8 imm:$src2)))]>, NDD<1>;
1260 …: BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>, Sched<[WriteALU.Folded, WriteALU.Read…
1280 : BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>,
1315 : ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1), m,
1317 [(set t.RegClass:$dst, (node t.RegClass:$src1, CL))]>, NDD<ndd> {
1330 : ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1), m, binop_cl_ndd_args,
1331 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), CL))]>, NDD<1> {
1339 : ITy<o, f, t, out, (ins t.RegClass:$src1), m, args, p>, Sched<[WriteALU]>;
1344 (outs t.RegClass:$dst),
1345 [(set t.RegClass:$dst, (node t.RegClass:$src1))]>, NDD<ndd>;
1350 (outs t.RegClass:$dst),
1351 [(set t.RegClass:$dst, (node t.RegClass:$src1)),
1363 : UnaryOpM<o, f, m, unaryop_ndd_args, t, (outs t.RegClass:$dst),
1364 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1)))]>,
1369 : UnaryOpM<o, f, m, unaryop_ndd_args, t, (outs t.RegClass:$dst),
1370 [(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1)))]>,