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Searched refs:RVLocs (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp37 const SmallVectorImpl<CCValAssign> &RVLocs,
267 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
269 CCState RetCCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCall()
386 return lowerCallResult(Chain, Glue, RVLocs, dl, DAG, InVals); in LowerCall()
392 const SmallVectorImpl<CCValAssign> &RVLocs, in lowerCallResult() argument
397 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in lowerCallResult()
398 const CCValAssign &VA = RVLocs[i]; in lowerCallResult()
618 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
619 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
638 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp441 SmallVectorImpl<CCValAssign> &RVLocs, in AnalyzeReturnValues() argument
609 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
610 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
624 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
631 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
635 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
641 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
642 CCValAssign &VA = RVLocs[i]; in LowerReturn()
819 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
820 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp524 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
525 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
537 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
540 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
550 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
551 CCValAssign &VA = RVLocs[i]; in LowerReturn()
770 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
771 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
777 for (unsigned I = 0; I != RVLocs.size(); ++I) { in LowerCallResult()
778 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp242 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
243 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
268 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_32() local
271 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
284 i != RVLocs.size(); in LowerReturn_32()
286 CCValAssign &VA = RVLocs[i]; in LowerReturn_32()
306 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
351 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_64() local
354 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_64()
368 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn_64()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2094 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
2095 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); in FinishCall()
2099 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
2102 MVT DestVT = RVLocs[0].getValVT(); in FinishCall()
2107 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2108 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2110 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2111 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2116 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); in FinishCall()
2117 MVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
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H A DARMISelLowering.cpp2203 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2204 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2209 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2210 CCValAssign VA = RVLocs[i]; in LowerCallResult()
2229 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
2243 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
2247 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
3225 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3226 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
3270 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp592 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
596 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
610 for (size_t i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
611 CCValAssign &VA = RVLocs[i]; in LowerReturn()
639 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
640 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCallResult()
652 for (auto &Val : RVLocs) { in LowerCallResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp682 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
683 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
771 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
772 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
776 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E; in LowerReturn()
778 CCValAssign &VA = RVLocs[I]; in LowerReturn()
852 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I], in LowerReturn()
857 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg()); in LowerReturn()
1128 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1129 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
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H A DX86CallLowering.cpp
H A DX86FastISel.cpp3623 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
3624 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, in fastLowerCall()
3630 for (unsigned i = 0; i != RVLocs.size(); ++i) { in fastLowerCall()
3631 CCValAssign &VA = RVLocs[i]; in fastLowerCall()
3673 CLI.NumResultRegs = RVLocs.size(); in fastLowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp944 const SmallVectorImpl<CCValAssign> &RVLocs, in LowerCallResult() argument
949 for (const CCValAssign &VA : RVLocs) { in LowerCallResult()
1006 SmallVector<CCValAssign, 16> RVLocs; in LowerCCCCallTo() local
1008 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCCCCallTo()
1106 return LowerCallResult(Chain, InGlue, RVLocs, dl, DAG, InVals); in LowerCCCCallTo()
1300 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1301 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1322 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1325 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
1342 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp138 SmallVector<CCValAssign, 16> RVLocs; in canLowerReturn() local
139 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in canLowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp71 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
72 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
371 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
374 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
384 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
385 CCValAssign &VA = RVLocs[i]; in LowerReturn()
777 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
778 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCall()
789 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCall()
790 CCValAssign &VA = RVLocs[i]; in LowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1488 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1489 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1491 CCValAssign &VA = RVLocs[0]; in finishCall()
1492 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); in finishCall()
1574 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
1575 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context); in fastLowerCall()
1577 if (RVLocs.size() > 1) in fastLowerCall()
H A DPPCISelLowering.cpp5364 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
5365 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
5374 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
5375 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
5385 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
7878 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
7879 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
7892 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
7893 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
7904 for (unsigned i = 0, RealResIdx = 0; i != RVLocs.size(); ++i, ++RealResIdx) { in LowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1604 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1605 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
1616 for (CCValAssign const &RVLoc : RVLocs) { in LowerCallResult()
1636 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1637 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1652 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1655 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
1670 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
1671 CCValAssign &VA = RVLocs[i]; in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1287 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1288 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1295 if (RVLocs.size() != 1) in finishCall()
1298 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
1308 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1309 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
H A DMipsISelLowering.cpp3683 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
3684 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
3693 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
3694 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
3697 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3698 RVLocs[i].getLocVT(), InGlue); in LowerCallResult()
3966 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3967 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
3999 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
4003 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp262 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
263 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
280 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
283 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
296 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
297 CCValAssign &VA = RVLocs[i]; in LowerReturn()
425 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
427 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
436 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
438 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp890 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
891 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
896 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
897 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
1067 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1068 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
1081 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1082 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
1094 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
1095 CCValAssign &VA = RVLocs[i]; in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp7573 SmallVector<CCValAssign> RVLocs; in LowerCall() local
7574 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCall()
7578 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCall()
7579 auto &VA = RVLocs[i]; in LowerCall()
7589 SDValue RetValue2 = DAG.getCopyFromReg(Chain, DL, RVLocs[++i].getLocReg(), in LowerCall()
7608 SmallVector<CCValAssign> RVLocs; in CanLowerReturn() local
7609 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
7628 SmallVector<CCValAssign> RVLocs; in LowerReturn() local
7631 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
7636 if (CallConv == CallingConv::GHC && !RVLocs.empty()) in LowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3111 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
3112 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
3116 for (unsigned i = 0; i != RVLocs.size(); ++i) { in finishCall()
3117 CCValAssign &VA = RVLocs[i]; in finishCall()
3133 CLI.NumResultRegs = RVLocs.size(); in finishCall()
H A DAArch64ISelLowering.h574 const SmallVectorImpl<CCValAssign> &RVLocs,
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp766 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
767 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp22783 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
22784 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCall()
22788 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCall()
22789 auto &VA = RVLocs[i]; in LowerCall()
22799 SDValue RetValue2 = DAG.getCopyFromReg(Chain, DL, RVLocs[++i].getLocReg(), in LowerCall()
22818 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
22819 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
22841 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
22844 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
22850 if (CallConv == CallingConv::GHC && !RVLocs.empty()) in LowerReturn()
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