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Searched refs:MT_BBP (Results 1 – 9 of 9) sorted by relevance

/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dpci_phy.c75 val = mt76_rr(dev, MT_BBP(AGC, 0)); in mt76x2_phy_set_antenna()
80 mt76_clear(dev, MT_BBP(IBI, 9), BIT(11)); in mt76x2_phy_set_antenna()
81 mt76_clear(dev, MT_BBP(TXBE, 5), 3); in mt76x2_phy_set_antenna()
83 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2); in mt76x2_phy_set_antenna()
85 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4); in mt76x2_phy_set_antenna()
91 mt76_clear(dev, MT_BBP(IBI, 9), BIT(11)); in mt76x2_phy_set_antenna()
92 mt76_rmw_field(dev, MT_BBP(TXBE, 5), 3, 1); in mt76x2_phy_set_antenna()
94 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1); in mt76x2_phy_set_antenna()
96 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1); in mt76x2_phy_set_antenna()
104 mt76_set(dev, MT_BBP(IBI, 9), BIT(11)); in mt76x2_phy_set_antenna()
[all …]
H A Dphy.c18 mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_high_lna_gain()
20 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain); in mt76x2_adjust_high_lna_gain()
28 gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_agc_gain()
30 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain); in mt76x2_adjust_agc_gain()
218 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) in mt76x2_phy_tssi_compensate()
265 mt76_wr(dev, MT_BBP(AGC, 8), in mt76x2_phy_set_gain_val()
267 mt76_wr(dev, MT_BBP(AGC, 9), in mt76x2_phy_set_gain_val()
301 mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211); in mt76x2_phy_update_channel_gain()
302 val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf; in mt76x2_phy_update_channel_gain()
307 mt76_wr(dev, MT_BBP(AGC, 26), val); in mt76x2_phy_update_channel_gain()
[all …]
H A Dmac.c27 mt76_rr(dev, MT_BBP(IBI, 12))) { in mt76x2_mac_stop()
37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
38 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
41 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
H A Dusb_phy.c145 mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); in mt76x2u_phy_set_channel()
161 mt76_wr(dev, MT_BBP(AGC, 61), 0xff64a4e2); in mt76x2u_phy_set_channel()
162 mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010); in mt76x2u_phy_set_channel()
163 mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404); in mt76x2u_phy_set_channel()
164 mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); in mt76x2u_phy_set_channel()
167 mt76_set(dev, MT_BBP(TXO, 4), BIT(25)); in mt76x2u_phy_set_channel()
168 mt76_set(dev, MT_BBP(RXO, 13), BIT(8)); in mt76x2u_phy_set_channel()
H A Dusb_mac.c135 !mt76_rr(dev, MT_BBP(IBI, 12))) { in mt76x2u_mac_stop()
143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_dfs.c148 mt76_wr(dev, MT_BBP(DFS, 36), data); in mt76x02_dfs_set_capture_mode_ctrl()
212 mt76_wr(dev, MT_BBP(DFS, 1), 0xf); in mt76x02_dfs_detector_reset()
254 mt76_wr(dev, MT_BBP(DFS, 0), data); in mt76x02_dfs_get_hw_pulse()
257 pulse->period = mt76_rr(dev, MT_BBP(DFS, 19)); in mt76x02_dfs_get_hw_pulse()
260 pulse->w1 = mt76_rr(dev, MT_BBP(DFS, 20)); in mt76x02_dfs_get_hw_pulse()
261 pulse->w2 = mt76_rr(dev, MT_BBP(DFS, 23)); in mt76x02_dfs_get_hw_pulse()
264 pulse->burst = mt76_rr(dev, MT_BBP(DFS, 22)); in mt76x02_dfs_get_hw_pulse()
376 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event()
381 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event()
383 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event()
[all …]
H A Dmt76x02_phy.c16 val = mt76_rr(dev, MT_BBP(AGC, 0)); in mt76x02_phy_set_rxpath()
28 mt76_wr(dev, MT_BBP(AGC, 0), val); in mt76x02_phy_set_rxpath()
30 val = mt76_rr(dev, MT_BBP(AGC, 0)); in mt76x02_phy_set_rxpath()
41 mt76_set(dev, MT_BBP(TXBE, 5), 0x3); in mt76x02_phy_set_txdac()
44 mt76_clear(dev, MT_BBP(TXBE, 5), 0x3); in mt76x02_phy_set_txdac()
143 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val); in mt76x02_phy_set_bw()
144 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val); in mt76x02_phy_set_bw()
145 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl); in mt76x02_phy_set_bw()
146 mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl); in mt76x02_phy_set_bw()
195 dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8), in mt76x02_init_agc_gain()
[all …]
H A Dmt76x02_mac.c1113 mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0), in mt76x02_edcca_init()
1120 mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); in mt76x02_edcca_init()
1124 mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464); in mt76x02_edcca_init()
H A Dmt76x02_regs.h619 #define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2)) macro