| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64.td | 46 // Named operands for MRS/MSR/TLBI/...
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| H A D | AArch64ISelLowering.h | 327 MRS, // MRS, also sets the flags via a glue. enumerator
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| H A D | AArch64ExpandPseudoInsts.cpp | 1451 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg) in expandMI()
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| H A D | AArch64SchedFalkorDetails.td | 1253 def : InstRW<[FalkorWr_1LD_3cyc], (instrs MRS, MOVbaseTLS)>;
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| H A D | AArch64SMEInstrInfo.td | 190 (MRS 0xde85)>;
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| H A D | AArch64SchedKryoDetails.td | 1648 (instrs MRS)>;
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| H A D | AArch64InstrInfo.td | 940 def AArch64mrs : SDNode<"AArch64ISD::MRS",
2010 def MRS : MRSI;
2016 (MRS imm:$id)>;
2058 def : Pat<(readcyclecounter), (MRS 0xdf02)>;
2064 PseudoInstExpansion<(MRS GPR64:$dst, 0xda20)>,
2075 PseudoInstExpansion<(MRS GPR64:$dst, 0xda21)>,
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| H A D | AArch64InstrInfo.cpp | 2009 BuildMI(MBB, MI, DL, get(AArch64::MRS)) in expandPostRAPseudo()
4791 BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg) in copyPhysReg()
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| H A D | AArch64SystemOperands.td | 655 // MRS/MSR (system register read/write) instruction options.
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| H A D | AArch64InstrFormats.td | 1772 // MRS/MSR system instructions. These have different operand classes because
1777 let DiagnosticType = "MRS";
1833 // The MRS is set as a NZCV setting instruction. Not all MRS instructions
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| H A D | AArch64ISelDAGToDAG.cpp | 3959 unsigned Opcode64Bit = AArch64::MRS; in tryReadRegister()
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| H A D | AArch64ISelLowering.cpp | 2721 MAKE_CASE(AArch64ISD::MRS) in getTargetNodeName()
25569 AArch64ISD::MRS, DL, DAG.getVTList(MVT::i64, MVT::Glue, MVT::Other), in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 401 // MSR/MRS
402 def : InstRW<[M7NonGeneralPurpose], (instregex "MSR", "MRS")>;
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| H A D | ARMScheduleR52.td | 342 def : InstRW<[R52WriteLd], (instregex "MRS", "MRSbanked")>;
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| H A D | ARMScheduleA57.td | 133 "(t2)?MRRC(2)?$", "(t2)?MRS(banked|sys|_AR|_M|sys_AR)?$",
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| H A D | ARMInstrInfo.td | 5779 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5791 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,
5794 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5808 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
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| H A D | ARMInstrThumb2.td | 4479 // A/R class MRS.
4517 // M class MRS.
4519 // This MRS has a mask field in bits 7-0 and can take more values than
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| H A D | ARMBaseInstrInfo.cpp | 834 : ARM::MRS; in copyFromCPSR()
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| H A D | ARMISelDAGToDAG.cpp | 5585 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
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| /freebsd/contrib/ntp/ |
| H A D | README.leapsmear | 260 precision=-18, rootdelay=0.000, rootdisp=1.075, refid=MRS,
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| /freebsd/contrib/file/magic/Magdir/ |
| H A D | wordprocessors | 123 # like: WP.MRS
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