1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// Subtarget features. 20//===----------------------------------------------------------------------===// 21include "AArch64Features.td" 22include "AArch64FMV.td" 23 24//===----------------------------------------------------------------------===// 25// Register File Description 26//===----------------------------------------------------------------------===// 27 28include "AArch64RegisterInfo.td" 29include "AArch64RegisterBanks.td" 30include "AArch64CallingConvention.td" 31 32//===----------------------------------------------------------------------===// 33// Instruction Descriptions 34//===----------------------------------------------------------------------===// 35 36include "AArch64Schedule.td" 37include "AArch64InstrInfo.td" 38include "AArch64SchedPredicates.td" 39include "AArch64SchedPredExynos.td" 40include "AArch64SchedPredNeoverse.td" 41include "AArch64Combine.td" 42 43def AArch64InstrInfo : InstrInfo; 44 45//===----------------------------------------------------------------------===// 46// Named operands for MRS/MSR/TLBI/... 47//===----------------------------------------------------------------------===// 48 49include "AArch64SystemOperands.td" 50 51//===----------------------------------------------------------------------===// 52// AArch64 Processors supported. 53// 54 55//===----------------------------------------------------------------------===// 56// Unsupported features to disable for scheduling models 57//===----------------------------------------------------------------------===// 58 59class AArch64Unsupported { list<Predicate> F; } 60 61let F = [HasSVE2p1, HasSVE2p1_or_HasSME2, HasSVE2p1_or_HasSME2p1] in 62def SVE2p1Unsupported : AArch64Unsupported; 63 64def SVE2Unsupported : AArch64Unsupported { 65 let F = !listconcat([HasSVE2, HasSVE2orSME, HasSVE2orSME2, HasSSVE_FP8FMA, HasSMEF8F16, 66 HasSMEF8F32, HasSVE2AES, HasSVE2SHA3, HasSVE2SM4, HasSVE2BitPerm], 67 SVE2p1Unsupported.F); 68} 69 70def SVEUnsupported : AArch64Unsupported { 71 let F = !listconcat([HasSVE, HasSVEorSME], 72 SVE2Unsupported.F); 73} 74 75let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1] in 76def SME2p1Unsupported : AArch64Unsupported; 77 78def SME2Unsupported : AArch64Unsupported { 79 let F = !listconcat([HasSME2, HasSVE2orSME2, HasSVE2p1_or_HasSME2, HasSSVE_FP8FMA, 80 HasSMEF8F16, HasSMEF8F32, HasSMEF16F16orSMEF8F16], 81 SME2p1Unsupported.F); 82} 83 84def SMEUnsupported : AArch64Unsupported { 85 let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64], 86 SME2Unsupported.F); 87} 88 89def MTEUnsupported : AArch64Unsupported { 90 let F = [HasMTE]; 91} 92 93let F = [HasPAuth, HasPAuthLR] in 94def PAUnsupported : AArch64Unsupported; 95 96include "AArch64SchedA53.td" 97include "AArch64SchedA55.td" 98include "AArch64SchedA510.td" 99include "AArch64SchedA57.td" 100include "AArch64SchedCyclone.td" 101include "AArch64SchedFalkor.td" 102include "AArch64SchedKryo.td" 103include "AArch64SchedExynosM3.td" 104include "AArch64SchedExynosM4.td" 105include "AArch64SchedExynosM5.td" 106include "AArch64SchedThunderX.td" 107include "AArch64SchedThunderX2T99.td" 108include "AArch64SchedA64FX.td" 109include "AArch64SchedThunderX3T110.td" 110include "AArch64SchedTSV110.td" 111include "AArch64SchedAmpere1.td" 112include "AArch64SchedAmpere1B.td" 113include "AArch64SchedNeoverseN1.td" 114include "AArch64SchedNeoverseN2.td" 115include "AArch64SchedNeoverseV1.td" 116include "AArch64SchedNeoverseV2.td" 117include "AArch64SchedOryon.td" 118 119include "AArch64Processors.td" 120 121//===----------------------------------------------------------------------===// 122// Assembly parser 123//===----------------------------------------------------------------------===// 124 125def GenericAsmParserVariant : AsmParserVariant { 126 int Variant = 0; 127 string Name = "generic"; 128 string BreakCharacters = "."; 129 string TokenizingCharacters = "[]*!/"; 130} 131 132def AppleAsmParserVariant : AsmParserVariant { 133 int Variant = 1; 134 string Name = "apple-neon"; 135 string BreakCharacters = "."; 136 string TokenizingCharacters = "[]*!/"; 137} 138 139//===----------------------------------------------------------------------===// 140// Assembly printer 141//===----------------------------------------------------------------------===// 142// AArch64 Uses the MC printer for asm output, so make sure the TableGen 143// AsmWriter bits get associated with the correct class. 144def GenericAsmWriter : AsmWriter { 145 string AsmWriterClassName = "InstPrinter"; 146 int PassSubtarget = 1; 147 int Variant = 0; 148 bit isMCAsmWriter = 1; 149} 150 151def AppleAsmWriter : AsmWriter { 152 let AsmWriterClassName = "AppleInstPrinter"; 153 int PassSubtarget = 1; 154 int Variant = 1; 155 int isMCAsmWriter = 1; 156} 157 158//===----------------------------------------------------------------------===// 159// Target Declaration 160//===----------------------------------------------------------------------===// 161 162def AArch64 : Target { 163 let InstructionSet = AArch64InstrInfo; 164 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 165 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 166 let AllowRegisterRenaming = 1; 167} 168 169//===----------------------------------------------------------------------===// 170// Pfm Counters 171//===----------------------------------------------------------------------===// 172 173include "AArch64PfmCounters.td" 174