1//===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the symbolic operands permitted for various kinds of 10// AArch64 system instruction. 11// 12//===----------------------------------------------------------------------===// 13 14include "llvm/TableGen/SearchableTable.td" 15 16//===----------------------------------------------------------------------===// 17// Features that, for the compiler, only enable system operands and PStates 18//===----------------------------------------------------------------------===// 19 20def HasCCPP : Predicate<"Subtarget->hasCCPP()">, 21 AssemblerPredicateWithAll<(all_of FeatureCCPP), "ccpp">; 22 23def HasPAN : Predicate<"Subtarget->hasPAN()">, 24 AssemblerPredicateWithAll<(all_of FeaturePAN), 25 "ARM v8.1 Privileged Access-Never extension">; 26 27def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, 28 AssemblerPredicateWithAll<(all_of FeaturePsUAO), 29 "ARM v8.2 UAO PState extension (psuao)">; 30 31def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">, 32 AssemblerPredicateWithAll<(all_of FeaturePAN_RWV), 33 "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">; 34 35def HasCONTEXTIDREL2 36 : Predicate<"Subtarget->hasCONTEXTIDREL2()">, 37 AssemblerPredicateWithAll<(all_of FeatureCONTEXTIDREL2), 38 "Target contains CONTEXTIDR_EL2 RW operand">; 39 40//===----------------------------------------------------------------------===// 41// AT (address translate) instruction options. 42//===----------------------------------------------------------------------===// 43 44class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm, 45 bits<3> op2> : SearchableTable { 46 let SearchableFields = ["Name", "Encoding"]; 47 let EnumValueField = "Encoding"; 48 49 string Name = name; 50 bits<14> Encoding; 51 let Encoding{13-11} = op1; 52 let Encoding{10-7} = crn; 53 let Encoding{6-3} = crm; 54 let Encoding{2-0} = op2; 55 code Requires = [{ {} }]; 56} 57 58def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>; 59def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>; 60def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>; 61def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>; 62def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>; 63def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>; 64def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>; 65def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>; 66def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>; 67def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>; 68def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>; 69def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>; 70 71let Requires = [{ {AArch64::FeaturePAN_RWV} }] in { 72def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>; 73def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>; 74} 75 76// v8.9a/v9.4a FEAT_ATS1A 77def : AT<"S1E1A", 0b000, 0b0111, 0b1001, 0b010>; 78def : AT<"S1E2A", 0b100, 0b0111, 0b1001, 0b010>; 79def : AT<"S1E3A", 0b110, 0b0111, 0b1001, 0b010>; 80 81//===----------------------------------------------------------------------===// 82// DMB/DSB (data barrier) instruction options. 83//===----------------------------------------------------------------------===// 84 85class DB<string name, bits<4> encoding> : SearchableTable { 86 let SearchableFields = ["Name", "Encoding"]; 87 let EnumValueField = "Encoding"; 88 89 string Name = name; 90 bits<4> Encoding = encoding; 91} 92 93def : DB<"oshld", 0x1>; 94def : DB<"oshst", 0x2>; 95def : DB<"osh", 0x3>; 96def : DB<"nshld", 0x5>; 97def : DB<"nshst", 0x6>; 98def : DB<"nsh", 0x7>; 99def : DB<"ishld", 0x9>; 100def : DB<"ishst", 0xa>; 101def : DB<"ish", 0xb>; 102def : DB<"ld", 0xd>; 103def : DB<"st", 0xe>; 104def : DB<"sy", 0xf>; 105 106class DBnXS<string name, bits<4> encoding, bits<5> immValue> : SearchableTable { 107 let SearchableFields = ["Name", "Encoding", "ImmValue"]; 108 let EnumValueField = "Encoding"; 109 110 string Name = name; 111 bits<4> Encoding = encoding; 112 bits<5> ImmValue = immValue; 113 code Requires = [{ {AArch64::FeatureXS} }]; 114} 115 116def : DBnXS<"oshnxs", 0x3, 0x10>; 117def : DBnXS<"nshnxs", 0x7, 0x14>; 118def : DBnXS<"ishnxs", 0xb, 0x18>; 119def : DBnXS<"synxs", 0xf, 0x1c>; 120 121//===----------------------------------------------------------------------===// 122// DC (data cache maintenance) instruction options. 123//===----------------------------------------------------------------------===// 124 125class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm, 126 bits<3> op2> : SearchableTable { 127 let SearchableFields = ["Name", "Encoding"]; 128 let EnumValueField = "Encoding"; 129 130 string Name = name; 131 bits<14> Encoding; 132 let Encoding{13-11} = op1; 133 let Encoding{10-7} = crn; 134 let Encoding{6-3} = crm; 135 let Encoding{2-0} = op2; 136 code Requires = [{ {} }]; 137} 138 139def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>; 140def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>; 141def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>; 142def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>; 143def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>; 144def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>; 145def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; 146def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; 147 148let Requires = [{ {AArch64::FeatureCCPP} }] in 149def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; 150 151let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in 152def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>; 153 154let Requires = [{ {AArch64::FeatureMTE} }] in { 155def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>; 156def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>; 157def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>; 158def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>; 159def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>; 160def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>; 161def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>; 162def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>; 163def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>; 164def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>; 165def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>; 166def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>; 167def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>; 168def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>; 169def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>; 170def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>; 171def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; 172def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>; 173} 174 175let Requires = [{ {AArch64::FeatureMEC} }] in { 176def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>; 177def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>; 178} 179 180//===----------------------------------------------------------------------===// 181// IC (instruction cache maintenance) instruction options. 182//===----------------------------------------------------------------------===// 183 184class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, 185 bit needsreg> : SearchableTable { 186 let SearchableFields = ["Name", "Encoding"]; 187 let EnumValueField = "Encoding"; 188 189 string Name = name; 190 bits<14> Encoding; 191 let Encoding{13-11} = op1; 192 let Encoding{10-7} = crn; 193 let Encoding{6-3} = crm; 194 let Encoding{2-0} = op2; 195 bit NeedsReg = needsreg; 196} 197 198def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>; 199def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>; 200def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>; 201 202//===----------------------------------------------------------------------===// 203// ISB (instruction-fetch barrier) instruction options. 204//===----------------------------------------------------------------------===// 205 206class ISB<string name, bits<4> encoding> : SearchableTable{ 207 let SearchableFields = ["Name", "Encoding"]; 208 let EnumValueField = "Encoding"; 209 210 string Name = name; 211 bits<4> Encoding; 212 let Encoding = encoding; 213} 214 215def : ISB<"sy", 0xf>; 216 217//===----------------------------------------------------------------------===// 218// TSB (Trace synchronization barrier) instruction options. 219//===----------------------------------------------------------------------===// 220 221class TSB<string name, bits<4> encoding> : SearchableTable{ 222 let SearchableFields = ["Name", "Encoding"]; 223 let EnumValueField = "Encoding"; 224 225 string Name = name; 226 bits<4> Encoding; 227 let Encoding = encoding; 228 229 code Requires = [{ {AArch64::FeatureTRACEV8_4} }]; 230} 231 232def : TSB<"csync", 0>; 233 234//===----------------------------------------------------------------------===// 235// PRFM (prefetch) instruction options. 236//===----------------------------------------------------------------------===// 237 238class PRFM<string type, bits<2> type_encoding, 239 string target, bits<2> target_encoding, 240 string policy, bits<1> policy_encoding> : SearchableTable { 241 let SearchableFields = ["Name", "Encoding"]; 242 let EnumValueField = "Encoding"; 243 244 string Name = type # target # policy; 245 bits<5> Encoding; 246 let Encoding{4-3} = type_encoding; 247 let Encoding{2-1} = target_encoding; 248 let Encoding{0} = policy_encoding; 249 250 code Requires = [{ {} }]; 251} 252 253def : PRFM<"pld", 0b00, "l1", 0b00, "keep", 0b0>; 254def : PRFM<"pld", 0b00, "l1", 0b00, "strm", 0b1>; 255def : PRFM<"pld", 0b00, "l2", 0b01, "keep", 0b0>; 256def : PRFM<"pld", 0b00, "l2", 0b01, "strm", 0b1>; 257def : PRFM<"pld", 0b00, "l3", 0b10, "keep", 0b0>; 258def : PRFM<"pld", 0b00, "l3", 0b10, "strm", 0b1>; 259let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 260def : PRFM<"pld", 0b00, "slc", 0b11, "keep", 0b0>; 261def : PRFM<"pld", 0b00, "slc", 0b11, "strm", 0b1>; 262} 263def : PRFM<"pli", 0b01, "l1", 0b00, "keep", 0b0>; 264def : PRFM<"pli", 0b01, "l1", 0b00, "strm", 0b1>; 265def : PRFM<"pli", 0b01, "l2", 0b01, "keep", 0b0>; 266def : PRFM<"pli", 0b01, "l2", 0b01, "strm", 0b1>; 267def : PRFM<"pli", 0b01, "l3", 0b10, "keep", 0b0>; 268def : PRFM<"pli", 0b01, "l3", 0b10, "strm", 0b1>; 269let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 270def : PRFM<"pli", 0b01, "slc", 0b11, "keep", 0b0>; 271def : PRFM<"pli", 0b01, "slc", 0b11, "strm", 0b1>; 272} 273def : PRFM<"pst", 0b10, "l1", 0b00, "keep", 0b0>; 274def : PRFM<"pst", 0b10, "l1", 0b00, "strm", 0b1>; 275def : PRFM<"pst", 0b10, "l2", 0b01, "keep", 0b0>; 276def : PRFM<"pst", 0b10, "l2", 0b01, "strm", 0b1>; 277def : PRFM<"pst", 0b10, "l3", 0b10, "keep", 0b0>; 278def : PRFM<"pst", 0b10, "l3", 0b10, "strm", 0b1>; 279let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 280def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>; 281def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>; 282} 283 284//===----------------------------------------------------------------------===// 285// SVE Prefetch instruction options. 286//===----------------------------------------------------------------------===// 287 288class SVEPRFM<string name, bits<4> encoding> : SearchableTable { 289 let SearchableFields = ["Name", "Encoding"]; 290 let EnumValueField = "Encoding"; 291 292 string Name = name; 293 bits<4> Encoding; 294 let Encoding = encoding; 295 code Requires = [{ {} }]; 296} 297 298let Requires = [{ {AArch64::FeatureSVE} }] in { 299def : SVEPRFM<"pldl1keep", 0x00>; 300def : SVEPRFM<"pldl1strm", 0x01>; 301def : SVEPRFM<"pldl2keep", 0x02>; 302def : SVEPRFM<"pldl2strm", 0x03>; 303def : SVEPRFM<"pldl3keep", 0x04>; 304def : SVEPRFM<"pldl3strm", 0x05>; 305def : SVEPRFM<"pstl1keep", 0x08>; 306def : SVEPRFM<"pstl1strm", 0x09>; 307def : SVEPRFM<"pstl2keep", 0x0a>; 308def : SVEPRFM<"pstl2strm", 0x0b>; 309def : SVEPRFM<"pstl3keep", 0x0c>; 310def : SVEPRFM<"pstl3strm", 0x0d>; 311} 312 313//===----------------------------------------------------------------------===// 314// RPRFM (prefetch) instruction options. 315//===----------------------------------------------------------------------===// 316 317class RPRFM<string name, bits<1> type_encoding, bits<5> policy_encoding> : SearchableTable { 318 let SearchableFields = ["Name", "Encoding"]; 319 let EnumValueField = "Encoding"; 320 321 string Name = name; 322 bits<6> Encoding; 323 let Encoding{0} = type_encoding; 324 let Encoding{5-1} = policy_encoding; 325 code Requires = [{ {} }]; 326} 327 328def : RPRFM<"pldkeep", 0b0, 0b00000>; 329def : RPRFM<"pstkeep", 0b1, 0b00000>; 330def : RPRFM<"pldstrm", 0b0, 0b00010>; 331def : RPRFM<"pststrm", 0b1, 0b00010>; 332 333//===----------------------------------------------------------------------===// 334// SVE Predicate patterns 335//===----------------------------------------------------------------------===// 336 337class SVEPREDPAT<string name, bits<5> encoding> : SearchableTable { 338 let SearchableFields = ["Name", "Encoding"]; 339 let EnumValueField = "Encoding"; 340 341 string Name = name; 342 bits<5> Encoding; 343 let Encoding = encoding; 344} 345 346def : SVEPREDPAT<"pow2", 0x00>; 347def : SVEPREDPAT<"vl1", 0x01>; 348def : SVEPREDPAT<"vl2", 0x02>; 349def : SVEPREDPAT<"vl3", 0x03>; 350def : SVEPREDPAT<"vl4", 0x04>; 351def : SVEPREDPAT<"vl5", 0x05>; 352def : SVEPREDPAT<"vl6", 0x06>; 353def : SVEPREDPAT<"vl7", 0x07>; 354def : SVEPREDPAT<"vl8", 0x08>; 355def : SVEPREDPAT<"vl16", 0x09>; 356def : SVEPREDPAT<"vl32", 0x0a>; 357def : SVEPREDPAT<"vl64", 0x0b>; 358def : SVEPREDPAT<"vl128", 0x0c>; 359def : SVEPREDPAT<"vl256", 0x0d>; 360def : SVEPREDPAT<"mul4", 0x1d>; 361def : SVEPREDPAT<"mul3", 0x1e>; 362def : SVEPREDPAT<"all", 0x1f>; 363 364//===----------------------------------------------------------------------===// 365// SVE Predicate-as-counter patterns 366//===----------------------------------------------------------------------===// 367 368class SVEVECLENSPECIFIER<string name, bits<1> encoding> : SearchableTable { 369 let SearchableFields = ["Name", "Encoding"]; 370 let EnumValueField = "Encoding"; 371 372 string Name = name; 373 bits<1> Encoding; 374 let Encoding = encoding; 375} 376 377def : SVEVECLENSPECIFIER<"vlx2", 0x0>; 378def : SVEVECLENSPECIFIER<"vlx4", 0x1>; 379 380//===----------------------------------------------------------------------===// 381// Exact FP Immediates. 382// 383// These definitions are used to create a lookup table with FP Immediates that 384// is used for a few instructions that only accept a limited set of exact FP 385// immediates values. 386//===----------------------------------------------------------------------===// 387class ExactFPImm<string name, string repr, bits<4> enum > : SearchableTable { 388 let SearchableFields = ["Enum", "Repr"]; 389 let EnumValueField = "Enum"; 390 391 string Name = name; 392 bits<4> Enum = enum; 393 string Repr = repr; 394} 395 396def : ExactFPImm<"zero", "0.0", 0x0>; 397def : ExactFPImm<"half", "0.5", 0x1>; 398def : ExactFPImm<"one", "1.0", 0x2>; 399def : ExactFPImm<"two", "2.0", 0x3>; 400 401//===----------------------------------------------------------------------===// 402// PState instruction options. 403//===----------------------------------------------------------------------===// 404 405class PStateImm0_15<string name, bits<3> op1, bits<3> op2> : SearchableTable { 406 let SearchableFields = ["Name", "Encoding"]; 407 let EnumValueField = "Encoding"; 408 409 string Name = name; 410 bits<6> Encoding; 411 let Encoding{5-3} = op1; 412 let Encoding{2-0} = op2; 413 code Requires = [{ {} }]; 414} 415 416class PStateImm0_1<string name, bits<3> op1, bits<3> op2, bits<3> crm_high> : SearchableTable { 417 let SearchableFields = ["Name", "Encoding"]; 418 let EnumValueField = "Encoding"; 419 420 string Name = name; 421 bits<9> Encoding; 422 let Encoding{8-6} = crm_high; 423 let Encoding{5-3} = op1; 424 let Encoding{2-0} = op2; 425 code Requires = [{ {} }]; 426} 427 428// Name, Op1, Op2 429def : PStateImm0_15<"SPSel", 0b000, 0b101>; 430def : PStateImm0_15<"DAIFSet", 0b011, 0b110>; 431def : PStateImm0_15<"DAIFClr", 0b011, 0b111>; 432// v8.1a "Privileged Access Never" extension-specific PStates 433let Requires = [{ {AArch64::FeaturePAN} }] in 434def : PStateImm0_15<"PAN", 0b000, 0b100>; 435 436// v8.2a "User Access Override" extension-specific PStates 437let Requires = [{ {AArch64::FeaturePsUAO} }] in 438def : PStateImm0_15<"UAO", 0b000, 0b011>; 439// v8.4a timing insensitivity of data processing instructions 440let Requires = [{ {AArch64::FeatureDIT} }] in 441def : PStateImm0_15<"DIT", 0b011, 0b010>; 442// v8.5a Spectre Mitigation 443let Requires = [{ {AArch64::FeatureSSBS} }] in 444def : PStateImm0_15<"SSBS", 0b011, 0b001>; 445// v8.5a Memory Tagging Extension 446let Requires = [{ {AArch64::FeatureMTE} }] in 447def : PStateImm0_15<"TCO", 0b011, 0b100>; 448// v8.8a Non-Maskable Interrupts 449let Requires = [{ {AArch64::FeatureNMI} }] in 450def : PStateImm0_1<"ALLINT", 0b001, 0b000, 0b000>; 451// v9.4a Exception-based event profiling 452// Name, Op1, Op2, Crm_high 453def : PStateImm0_1<"PM", 0b001, 0b000, 0b001>; 454 455//===----------------------------------------------------------------------===// 456// SVCR instruction options. 457//===----------------------------------------------------------------------===// 458 459class SVCR<string name, bits<3> encoding> : SearchableTable { 460 let SearchableFields = ["Name", "Encoding"]; 461 let EnumValueField = "Encoding"; 462 463 string Name = name; 464 bits<3> Encoding; 465 let Encoding = encoding; 466 code Requires = [{ {} }]; 467} 468 469let Requires = [{ {AArch64::FeatureSME} }] in { 470def : SVCR<"SVCRSM", 0b001>; 471def : SVCR<"SVCRZA", 0b010>; 472def : SVCR<"SVCRSMZA", 0b011>; 473} 474 475//===----------------------------------------------------------------------===// 476// PSB instruction options. 477//===----------------------------------------------------------------------===// 478 479class PSB<string name, bits<5> encoding> : SearchableTable { 480 let SearchableFields = ["Name", "Encoding"]; 481 let EnumValueField = "Encoding"; 482 483 string Name = name; 484 bits<5> Encoding; 485 let Encoding = encoding; 486} 487 488def : PSB<"csync", 0x11>; 489 490//===----------------------------------------------------------------------===// 491// BTI instruction options. 492//===----------------------------------------------------------------------===// 493 494class BTI<string name, bits<3> encoding> : SearchableTable { 495 let SearchableFields = ["Name", "Encoding"]; 496 let EnumValueField = "Encoding"; 497 498 string Name = name; 499 bits<3> Encoding; 500 let Encoding = encoding; 501} 502 503def : BTI<"c", 0b010>; 504def : BTI<"j", 0b100>; 505def : BTI<"jc", 0b110>; 506 507//===----------------------------------------------------------------------===// 508// TLBI (translation lookaside buffer invalidate) instruction options. 509//===----------------------------------------------------------------------===// 510 511class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm, 512 bits<3> op2, bit needsreg> { 513 string Name = name; 514 bits<14> Encoding; 515 let Encoding{13-11} = op1; 516 let Encoding{10-7} = crn; 517 let Encoding{6-3} = crm; 518 let Encoding{2-0} = op2; 519 bit NeedsReg = needsreg; 520 list<string> Requires = []; 521 list<string> ExtraRequires = []; 522 code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }]; 523} 524 525def TLBITable : GenericTable { 526 let FilterClass = "TLBIEntry"; 527 let CppTypeName = "TLBI"; 528 let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"]; 529} 530 531def lookupTLBIByName : SearchIndex { 532 let Table = TLBITable; 533 let Key = ["Name"]; 534} 535 536def lookupTLBIByEncoding : SearchIndex { 537 let Table = TLBITable; 538 let Key = ["Encoding"]; 539} 540 541multiclass TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, 542 bits<3> op2, bit needsreg = 1> { 543 def : TLBIEntry<name, op1, crn, crm, op2, needsreg>; 544 def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> { 545 let Encoding{7} = 1; 546 let ExtraRequires = ["AArch64::FeatureXS"]; 547 } 548} 549 550defm : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>; 551defm : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>; 552defm : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>; 553defm : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>; 554defm : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>; 555defm : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>; 556defm : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>; 557defm : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>; 558defm : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>; 559defm : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>; 560defm : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>; 561defm : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>; 562defm : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>; 563defm : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>; 564defm : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>; 565defm : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>; 566defm : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>; 567defm : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>; 568defm : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>; 569defm : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>; 570defm : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>; 571defm : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>; 572defm : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>; 573defm : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>; 574defm : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>; 575defm : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>; 576defm : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>; 577defm : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>; 578defm : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>; 579defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>; 580defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; 581defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; 582 583// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI) 584let Requires = ["AArch64::FeatureTLB_RMI"] in { 585// Armv8.4-A Outer Sharable TLB Maintenance instructions: 586// op1 CRn CRm op2 587defm : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>; 588defm : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>; 589defm : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>; 590defm : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>; 591defm : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>; 592defm : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>; 593defm : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>; 594defm : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>; 595defm : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>; 596defm : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>; 597defm : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>; 598defm : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>; 599defm : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>; 600defm : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>; 601defm : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>; 602defm : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>; 603 604// Armv8.4-A TLB Range Maintenance instructions: 605// op1 CRn CRm op2 606defm : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>; 607defm : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>; 608defm : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>; 609defm : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>; 610defm : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>; 611defm : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>; 612defm : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>; 613defm : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>; 614defm : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>; 615defm : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>; 616defm : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>; 617defm : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>; 618defm : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>; 619defm : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>; 620defm : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>; 621defm : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>; 622defm : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>; 623defm : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>; 624defm : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>; 625defm : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>; 626defm : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>; 627defm : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>; 628defm : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>; 629defm : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>; 630defm : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>; 631defm : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>; 632defm : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>; 633defm : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>; 634defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; 635defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; 636} //FeatureTLB_RMI 637 638// Armv9-A Realm Management Extention TLBI Instructions 639let Requires = ["AArch64::FeatureRME"] in { 640defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>; 641defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>; 642defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>; 643defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>; 644} 645 646// Armv9.5-A TLBI VMALL for Dirty State 647let Requires = ["AArch64::FeatureTLBIW"] in { 648// op1, CRn, CRm, op2, needsreg 649defm : TLBI<"VMALLWS2E1", 0b100, 0b1000, 0b0110, 0b010, 0>; 650defm : TLBI<"VMALLWS2E1IS", 0b100, 0b1000, 0b0010, 0b010, 0>; 651defm : TLBI<"VMALLWS2E1OS", 0b100, 0b1000, 0b0101, 0b010, 0>; 652} 653 654//===----------------------------------------------------------------------===// 655// MRS/MSR (system register read/write) instruction options. 656//===----------------------------------------------------------------------===// 657 658class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 659 bits<3> op2> : SearchableTable { 660 let SearchableFields = ["Name", "Encoding"]; 661 let EnumValueField = "Encoding"; 662 663 string Name = name; 664 string AltName = name; 665 bits<16> Encoding; 666 let Encoding{15-14} = op0; 667 let Encoding{13-11} = op1; 668 let Encoding{10-7} = crn; 669 let Encoding{6-3} = crm; 670 let Encoding{2-0} = op2; 671 bit Readable = ?; 672 bit Writeable = ?; 673 code Requires = [{ {} }]; 674} 675 676class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 677 bits<3> op2> 678 : SysReg<name, op0, op1, crn, crm, op2> { 679 let Readable = 1; 680 let Writeable = 1; 681} 682 683class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 684 bits<3> op2> 685 : SysReg<name, op0, op1, crn, crm, op2> { 686 let Readable = 1; 687 let Writeable = 0; 688} 689 690class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 691 bits<3> op2> 692 : SysReg<name, op0, op1, crn, crm, op2> { 693 let Readable = 0; 694 let Writeable = 1; 695} 696 697//===---------------------- 698// Read-only regs 699//===---------------------- 700 701// Op0 Op1 CRn CRm Op2 702def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>; 703def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 704def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>; 705def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>; 706def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; 707def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; 708def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; 709def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>; 710def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; 711def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; 712 713//v8.3 CCIDX - extending the CCsIDr number of sets 714def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> { 715 let Requires = [{ {AArch64::FeatureCCIDX} }]; 716} 717def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; 718def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>; 719def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>; 720def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>; 721def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>; 722def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>; 723def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>; 724def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>; 725def : ROSysReg<"ID_PFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b100> { 726 let Requires = [{ {AArch64::FeatureSpecRestrict} }]; 727} 728def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; 729def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>; 730def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; 731def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; 732def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; 733def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>; 734def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>; 735def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>; 736def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>; 737def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>; 738def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>; 739def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>; 740def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>; 741def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> { 742 let Requires = [{ {AArch64::HasV8_2aOps} }]; 743} 744def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>; 745def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>; 746def : ROSysReg<"ID_AA64PFR2_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b010>; 747def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>; 748def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>; 749def : ROSysReg<"ID_AA64DFR2_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b010>; 750def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>; 751def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; 752def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; 753def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; 754def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>; 755def : ROSysReg<"ID_AA64ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b011>; 756def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; 757def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; 758def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>; 759def : ROSysReg<"ID_AA64MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b011>; 760def : ROSysReg<"ID_AA64MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b100>; 761def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>; 762def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>; 763def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; 764def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>; 765def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>; 766def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>; 767def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; 768def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; 769def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; 770def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; 771def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>; 772 773// Trace registers 774// Op0 Op1 CRn CRm Op2 775def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>; 776def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>; 777def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>; 778def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>; 779def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>; 780def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>; 781def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>; 782def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>; 783def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>; 784def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>; 785def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>; 786def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>; 787def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>; 788def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; 789def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>; 790def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>; 791def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>; 792def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>; 793def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>; 794def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>; 795def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>; 796def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>; 797def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>; 798def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>; 799def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>; 800def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>; 801def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>; 802def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>; 803def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>; 804def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>; 805def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>; 806def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>; 807def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>; 808def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>; 809def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>; 810def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>; 811 812// GICv3 registers 813// Op0 Op1 CRn CRm Op2 814def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>; 815def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>; 816def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>; 817def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>; 818def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>; 819def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; 820def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; 821def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; 822 823// SVE control registers 824// Op0 Op1 CRn CRm Op2 825let Requires = [{ {AArch64::FeatureSVE} }] in { 826def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; 827} 828 829// v8.1a "Limited Ordering Regions" extension-specific system register 830// Op0 Op1 CRn CRm Op2 831let Requires = [{ {AArch64::FeatureLOR} }] in 832def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>; 833 834// v8.2a "RAS extension" registers 835// Op0 Op1 CRn CRm Op2 836let Requires = [{ {AArch64::FeatureRAS} }] in { 837def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>; 838def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>; 839} 840 841// v8.5a "random number" registers 842// Op0 Op1 CRn CRm Op2 843let Requires = [{ {AArch64::FeatureRandGen} }] in { 844def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>; 845def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>; 846} 847 848// v8.5a Software Context Number registers 849let Requires = [{ {AArch64::FeatureSpecRestrict} }] in { 850def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>; 851def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>; 852def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>; 853def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>; 854def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>; 855} 856 857// v9a Realm Management Extension registers 858let Requires = [{ {AArch64::FeatureRME} }] in { 859def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>; 860def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>; 861} 862// MFAR_EL3 is part of both FEAT_RME and FEAT_PFAR (further below). The latter 863// is unconditional so this register has to be too. 864def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>; 865 866// v9a Memory Encryption Contexts Extension registers 867let Requires = [{ {AArch64::FeatureMEC} }] in { 868def : ROSysReg<"MECIDR_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b111>; 869def : RWSysReg<"MECID_P0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b000>; 870def : RWSysReg<"MECID_A0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b001>; 871def : RWSysReg<"MECID_P1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b010>; 872def : RWSysReg<"MECID_A1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b011>; 873def : RWSysReg<"VMECID_P_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b000>; 874def : RWSysReg<"VMECID_A_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b001>; 875def : RWSysReg<"MECID_RL_A_EL3", 0b11, 0b110, 0b1010, 0b1010, 0b001>; 876} 877 878// v9-a Scalable Matrix Extension (SME) registers 879// Op0 Op1 CRn CRm Op2 880let Requires = [{ {AArch64::FeatureSME} }] in { 881def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>; 882} 883 884//===---------------------- 885// Write-only regs 886//===---------------------- 887 888// Op0 Op1 CRn CRm Op2 889def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 890def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>; 891def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>; 892 893// Trace Registers 894// Op0 Op1 CRn CRm Op2 895def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>; 896def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>; 897 898// GICv3 registers 899// Op0 Op1 CRn CRm Op2 900def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>; 901def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>; 902def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>; 903def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>; 904def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>; 905def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>; 906 907//===---------------------- 908// Read-write regs 909//===---------------------- 910 911// Op0 Op1 CRn CRm Op2 912def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>; 913def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>; 914def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>; 915def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>; 916def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>; 917def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>; 918def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>; 919def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>; 920foreach n = 0-15 in { 921 defvar nb = !cast<bits<4>>(n); 922 // Op0 Op1 CRn CRm Op2 923 def : RWSysReg<"DBGBVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b100>; 924 def : RWSysReg<"DBGBCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b101>; 925 def : RWSysReg<"DBGWVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b110>; 926 def : RWSysReg<"DBGWCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b111>; 927} 928// Op0 Op1 CRn CRm Op2 929def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>; 930def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>; 931def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>; 932def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>; 933def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>; 934def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>; 935def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>; 936def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>; 937def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>; 938def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>; 939def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>; 940def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>; 941def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>; 942def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>; 943def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>; 944def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>; 945def : RWSysReg<"HCRX_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b010> { 946 let Requires = [{ {AArch64::FeatureHCX} }]; 947} 948def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>; 949def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>; 950def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>; 951def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>; 952def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>; 953def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>; 954def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>; 955def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>; 956def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>; 957def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>; 958 959let Requires = [{ {AArch64::FeatureEL2VMSA} }] in { 960def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { 961 let AltName = "VSCTLR_EL2"; 962} 963def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; 964} 965 966def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>; 967def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>; 968def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>; 969def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>; 970def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>; 971def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>; 972def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>; 973def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>; 974def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>; 975def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>; 976def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>; 977def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>; 978def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>; 979def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>; 980def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>; 981def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>; 982def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>; 983def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>; 984def : ROSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>; 985def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>; 986def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>; 987def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>; 988def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>; 989let Requires = [{ {AArch64::FeatureFPARMv8} }] in { 990def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>; 991def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>; 992} 993def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>; 994def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>; 995def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>; 996def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>; 997def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>; 998def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>; 999def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>; 1000def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>; 1001def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>; 1002def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>; 1003def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>; 1004def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>; 1005def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>; 1006def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>; 1007def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>; 1008def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>; 1009def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>; 1010def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>; 1011def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>; 1012def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>; 1013def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>; 1014def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>; 1015def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>; 1016def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>; 1017def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>; 1018def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>; 1019def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>; 1020def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>; 1021def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>; 1022def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>; 1023def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>; 1024def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>; 1025def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>; 1026def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>; 1027def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>; 1028def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>; 1029def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>; 1030def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>; 1031def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>; 1032def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>; 1033def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>; 1034def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>; 1035def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>; 1036def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>; 1037def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>; 1038def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>; 1039def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>; 1040def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>; 1041def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>; 1042def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>; 1043def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>; 1044def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>; 1045def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>; 1046def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>; 1047def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>; 1048def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>; 1049def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>; 1050def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>; 1051def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>; 1052def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>; 1053def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>; 1054def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>; 1055def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>; 1056def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>; 1057def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>; 1058def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>; 1059def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>; 1060def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>; 1061def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>; 1062def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>; 1063def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>; 1064def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>; 1065def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>; 1066def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>; 1067def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>; 1068def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>; 1069def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>; 1070def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>; 1071def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>; 1072def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>; 1073def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>; 1074def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>; 1075def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>; 1076def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>; 1077def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>; 1078def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>; 1079def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>; 1080def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>; 1081def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>; 1082def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>; 1083def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>; 1084def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>; 1085def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>; 1086def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>; 1087def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>; 1088def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>; 1089def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>; 1090def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>; 1091def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>; 1092def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>; 1093def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>; 1094def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>; 1095def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>; 1096def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>; 1097def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>; 1098def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>; 1099def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>; 1100def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>; 1101def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>; 1102def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>; 1103def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>; 1104def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>; 1105def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>; 1106def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>; 1107def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>; 1108def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>; 1109def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>; 1110def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>; 1111def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>; 1112def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>; 1113def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>; 1114def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>; 1115def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>; 1116def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>; 1117def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>; 1118def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>; 1119def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>; 1120 1121// Trace registers 1122// Op0 Op1 CRn CRm Op2 1123def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>; 1124def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>; 1125def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>; 1126def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>; 1127def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>; 1128def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>; 1129def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>; 1130def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>; 1131def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>; 1132def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>; 1133def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>; 1134def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>; 1135def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>; 1136def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>; 1137def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>; 1138def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>; 1139def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>; 1140def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>; 1141def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>; 1142def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>; 1143def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>; 1144def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>; 1145def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>; 1146def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>; 1147def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>; 1148def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1149def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>; 1150def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>; 1151def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>; 1152def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>; 1153def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>; 1154def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>; 1155def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>; 1156def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>; 1157def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>; 1158def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>; 1159def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>; 1160def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>; 1161def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>; 1162def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>; 1163def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>; 1164def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>; 1165def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>; 1166def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>; 1167def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>; 1168def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>; 1169def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>; 1170def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>; 1171def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>; 1172def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>; 1173def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>; 1174def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>; 1175def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>; 1176def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>; 1177def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>; 1178def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>; 1179def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>; 1180def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>; 1181def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>; 1182def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>; 1183def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>; 1184def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>; 1185def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>; 1186def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>; 1187def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>; 1188def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>; 1189def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>; 1190def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>; 1191def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>; 1192def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>; 1193def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>; 1194def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>; 1195def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>; 1196def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>; 1197def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>; 1198def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>; 1199def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>; 1200def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>; 1201def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>; 1202def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>; 1203def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>; 1204def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>; 1205def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>; 1206def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>; 1207def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>; 1208def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>; 1209def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>; 1210def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>; 1211def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>; 1212def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>; 1213def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>; 1214def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>; 1215def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>; 1216def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>; 1217def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>; 1218def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>; 1219def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>; 1220def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>; 1221def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>; 1222def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>; 1223def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>; 1224def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>; 1225def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>; 1226def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>; 1227def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>; 1228def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>; 1229def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>; 1230def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>; 1231def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>; 1232def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>; 1233def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>; 1234def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>; 1235def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>; 1236def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>; 1237def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>; 1238def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>; 1239def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>; 1240def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>; 1241def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>; 1242def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>; 1243def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>; 1244def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>; 1245def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>; 1246def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>; 1247def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>; 1248def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>; 1249def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>; 1250def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>; 1251def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>; 1252def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>; 1253def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>; 1254def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>; 1255def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>; 1256def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>; 1257def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>; 1258def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>; 1259def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>; 1260def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>; 1261def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>; 1262def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>; 1263def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>; 1264def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>; 1265def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>; 1266def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>; 1267def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>; 1268def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>; 1269def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>; 1270def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>; 1271def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>; 1272def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>; 1273def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>; 1274def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>; 1275def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>; 1276def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>; 1277def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>; 1278def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>; 1279def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>; 1280def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>; 1281def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>; 1282def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>; 1283def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>; 1284def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>; 1285def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>; 1286def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>; 1287def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>; 1288def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>; 1289def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>; 1290def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>; 1291def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>; 1292def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>; 1293def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>; 1294def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>; 1295 1296// GICv3 registers 1297// Op0 Op1 CRn CRm Op2 1298def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>; 1299def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>; 1300def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>; 1301def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>; 1302def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>; 1303def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>; 1304def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>; 1305def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>; 1306def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>; 1307def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>; 1308def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>; 1309def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>; 1310def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>; 1311def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>; 1312def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>; 1313def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>; 1314def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>; 1315def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>; 1316def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>; 1317def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>; 1318def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>; 1319def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>; 1320def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>; 1321def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>; 1322def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>; 1323def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>; 1324def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>; 1325def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>; 1326def : ROSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>; 1327def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>; 1328def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>; 1329def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>; 1330def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>; 1331def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>; 1332def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>; 1333def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>; 1334def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>; 1335def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>; 1336def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>; 1337def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>; 1338def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>; 1339def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>; 1340def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>; 1341def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>; 1342def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; 1343def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; 1344 1345// v8r system registers 1346let Requires = [{ {AArch64::HasV8_0rOps} }] in { 1347//Virtualization System Control Register 1348// Op0 Op1 CRn CRm Op2 1349def : RWSysReg<"VSCTLR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000> { 1350 let AltName = "TTBR0_EL2"; 1351} 1352 1353//MPU Type Register 1354// Op0 Op1 CRn CRm Op2 1355def : RWSysReg<"MPUIR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b100>; 1356def : RWSysReg<"MPUIR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b100>; 1357 1358//Protection Region Enable Register 1359// Op0 Op1 CRn CRm Op2 1360def : RWSysReg<"PRENR_EL1", 0b11, 0b000, 0b0110, 0b0001, 0b001>; 1361def : RWSysReg<"PRENR_EL2", 0b11, 0b100, 0b0110, 0b0001, 0b001>; 1362 1363//Protection Region Selection Register 1364// Op0 Op1 CRn CRm Op2 1365def : RWSysReg<"PRSELR_EL1", 0b11, 0b000, 0b0110, 0b0010, 0b001>; 1366def : RWSysReg<"PRSELR_EL2", 0b11, 0b100, 0b0110, 0b0010, 0b001>; 1367 1368//Protection Region Base Address Register 1369// Op0 Op1 CRn CRm Op2 1370def : RWSysReg<"PRBAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b000>; 1371def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>; 1372 1373//Protection Region Limit Address Register 1374// Op0 Op1 CRn CRm Op2 1375def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>; 1376def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>; 1377 1378foreach n = 1-15 in { 1379foreach x = 1-2 in { 1380//Direct acces to Protection Region Base Address Register for n th MPU region 1381 def : RWSysReg<!strconcat("PRBAR"#n, "_EL"#x), 1382 0b11, 0b000, 0b0110, 0b1000, 0b000>{ 1383 let Encoding{5-2} = n; 1384 let Encoding{13} = !add(x,-1); 1385 } 1386 1387 def : RWSysReg<!strconcat("PRLAR"#n, "_EL"#x), 1388 0b11, 0b000, 0b0110, 0b1000, 0b001>{ 1389 let Encoding{5-2} = n; 1390 let Encoding{13} = !add(x,-1); 1391 } 1392} //foreach x = 1-2 in 1393} //foreach n = 1-15 in 1394} //let Requires = [{ {AArch64::HasV8_0rOps} }] in 1395 1396// v8.1a "Privileged Access Never" extension-specific system registers 1397let Requires = [{ {AArch64::FeaturePAN} }] in 1398def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; 1399 1400// v8.1a "Limited Ordering Regions" extension-specific system registers 1401// Op0 Op1 CRn CRm Op2 1402let Requires = [{ {AArch64::FeatureLOR} }] in { 1403def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>; 1404def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>; 1405def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>; 1406def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>; 1407} 1408 1409// v8.1a "Virtualization Host extensions" system registers 1410// Op0 Op1 CRn CRm Op2 1411let Requires = [{ {AArch64::FeatureVH} }] in { 1412def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>; 1413def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>; 1414def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>; 1415def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>; 1416def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>; 1417def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>; 1418def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>; 1419def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>; 1420def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>; 1421def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>; 1422def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>; 1423def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>; 1424def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>; 1425def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>; 1426def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>; 1427def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>; 1428def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>; 1429def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>; 1430def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>; 1431def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>; 1432def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>; 1433def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>; 1434def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>; 1435def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>; 1436def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>; 1437def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>; 1438let Requires = [{ {AArch64::FeatureCONTEXTIDREL2} }] in { 1439 def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>; 1440} 1441} 1442// v8.2a registers 1443// Op0 Op1 CRn CRm Op2 1444let Requires = [{ {AArch64::FeaturePsUAO} }] in 1445def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>; 1446 1447// v8.2a "Statistical Profiling extension" registers 1448// Op0 Op1 CRn CRm Op2 1449let Requires = [{ {AArch64::FeatureSPE} }] in { 1450def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>; 1451def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>; 1452def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>; 1453def : ROSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>; 1454def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>; 1455def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>; 1456def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>; 1457def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>; 1458def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>; 1459def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>; 1460def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>; 1461def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>; 1462def : ROSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>; 1463} 1464 1465// v8.2a "RAS extension" registers 1466// Op0 Op1 CRn CRm Op2 1467let Requires = [{ {AArch64::FeatureRAS} }] in { 1468def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>; 1469def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>; 1470def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>; 1471def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>; 1472def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>; 1473def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>; 1474def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>; 1475def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>; 1476def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; 1477} 1478 1479// v8.3a "Pointer authentication extension" registers 1480// Op0 Op1 CRn CRm Op2 1481let Requires = [{ {AArch64::FeaturePAuth} }] in { 1482def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; 1483def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; 1484def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; 1485def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>; 1486def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>; 1487def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>; 1488def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>; 1489def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>; 1490def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>; 1491def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; 1492} 1493 1494// v8.4 "Secure Exception Level 2 extension" 1495let Requires = [{ {AArch64::FeatureSEL2} }] in { 1496// v8.4a "Virtualization secure second stage translation" registers 1497// Op0 Op1 CRn CRm Op2 1498def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; 1499def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> { 1500 let Requires = [{ {AArch64::HasV8_0aOps} }]; 1501} 1502 1503// v8.4a "Virtualization timer" registers 1504// Op0 Op1 CRn CRm Op2 1505def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>; 1506def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>; 1507def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>; 1508def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>; 1509def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>; 1510def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; 1511 1512// v8.4a "Virtualization debug state" registers 1513// Op0 Op1 CRn CRm Op2 1514def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; 1515} // FeatureSEL2 1516 1517// v8.4a RAS registers 1518// Op0 Op1 CRn CRm Op2 1519def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>; 1520def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>; 1521def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>; 1522def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>; 1523def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>; 1524 1525// v8.4a MPAM registers 1526// Op0 Op1 CRn CRm Op2 1527let Requires = [{ {AArch64::FeatureMPAM} }] in { 1528def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>; 1529def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>; 1530def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>; 1531def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>; 1532def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>; 1533def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>; 1534def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>; 1535def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>; 1536def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>; 1537def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>; 1538def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>; 1539def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>; 1540def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>; 1541def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>; 1542def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>; 1543def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>; 1544} //FeatureMPAM 1545 1546// v8.4a Activity Monitor registers 1547// Op0 Op1 CRn CRm Op2 1548let Requires = [{ {AArch64::FeatureAM} }] in { 1549def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>; 1550def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>; 1551def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>; 1552def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>; 1553def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>; 1554def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>; 1555def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>; 1556def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>; 1557def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>; 1558def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>; 1559def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>; 1560def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>; 1561def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>; 1562def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>; 1563def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>; 1564def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>; 1565def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>; 1566def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>; 1567def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>; 1568def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>; 1569def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>; 1570def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>; 1571def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>; 1572def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>; 1573def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>; 1574def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>; 1575def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>; 1576def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>; 1577def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>; 1578def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>; 1579def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>; 1580def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>; 1581def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>; 1582def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>; 1583def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>; 1584def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>; 1585def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>; 1586def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>; 1587def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>; 1588def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>; 1589def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>; 1590def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>; 1591def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>; 1592def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>; 1593def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>; 1594def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>; 1595def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>; 1596def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>; 1597} //FeatureAM 1598 1599// v8.4a Trace Extension registers 1600// 1601// Please note that the 8.4 spec also defines these registers: 1602// TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3, 1603// but they are already defined above. 1604// 1605// Op0 Op1 CRn CRm Op2 1606let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in { 1607def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>; 1608def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>; 1609def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>; 1610} //FeatureTRACEV8_4 1611 1612// v8.4a Timing insensitivity of data processing instructions 1613// DIT: Data Independent Timing instructions 1614// Op0 Op1 CRn CRm Op2 1615let Requires = [{ {AArch64::FeatureDIT} }] in { 1616def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>; 1617} //FeatureDIT 1618 1619// v8.4a Enhanced Support for Nested Virtualization 1620// Op0 Op1 CRn CRm Op2 1621let Requires = [{ {AArch64::FeatureNV} }] in { 1622def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>; 1623} //FeatureNV 1624 1625// SVE control registers 1626// Op0 Op1 CRn CRm Op2 1627let Requires = [{ {AArch64::FeatureSVE} }] in { 1628def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>; 1629def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>; 1630def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>; 1631def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; 1632} 1633 1634// V8.5a Spectre mitigation SSBS register 1635// Op0 Op1 CRn CRm Op2 1636let Requires = [{ {AArch64::FeatureSSBS} }] in 1637def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>; 1638 1639// v8.5a Memory Tagging Extension 1640// Op0 Op1 CRn CRm Op2 1641let Requires = [{ {AArch64::FeatureMTE} }] in { 1642def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>; 1643def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>; 1644def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>; 1645def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>; 1646def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>; 1647def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>; 1648def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>; 1649def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>; 1650def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>; 1651} // HasMTE 1652 1653// Embedded Trace Extension R/W System registers 1654let Requires = [{ {AArch64::FeatureETE} }] in { 1655// Name Op0 Op1 CRn CRm Op2 1656def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>; 1657// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR 1658def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1659def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>; 1660def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>; 1661def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>; 1662} // FeatureETE 1663 1664// Trace Buffer Extension System registers 1665let Requires = [{ {AArch64::FeatureTRBE} }] in { 1666// Name Op0 Op1 CRn CRm Op2 1667def : RWSysReg<"TRBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b000>; 1668def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>; 1669def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>; 1670def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>; 1671def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>; 1672def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>; 1673def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>; 1674} // FeatureTRBE 1675 1676 1677// v8.6a Activity Monitors Virtualization Support 1678let Requires = [{ {AArch64::FeatureAMVS} }] in { 1679// Name Op0 Op1 CRn CRm Op2 1680def : ROSysReg<"AMCG1IDR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b110>; 1681foreach n = 0-15 in { 1682 foreach x = 0-1 in { 1683 def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2", 1684 0b11, 0b100, 0b1101, 0b1000, 0b000>{ 1685 let Encoding{4} = x; 1686 let Encoding{3-0} = n; 1687 } 1688 } 1689} 1690} 1691 1692// v8.6a Fine Grained Virtualization Traps 1693// Op0 Op1 CRn CRm Op2 1694let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in { 1695def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>; 1696def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>; 1697def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>; 1698def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>; 1699def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>; 1700def : RWSysReg<"HAFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b110>; 1701 1702// v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2) 1703// Op0 Op1 CRn CRm Op2 1704def : RWSysReg<"HDFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b000>; 1705def : RWSysReg<"HDFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b001>; 1706def : RWSysReg<"HFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b010>; 1707def : RWSysReg<"HFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b011>; 1708def : RWSysReg<"HFGITR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b111>; 1709} 1710 1711// v8.6a Enhanced Counter Virtualization 1712// Op0 Op1 CRn CRm Op2 1713let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in { 1714def : RWSysReg<"CNTSCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b100>; 1715def : RWSysReg<"CNTISCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b101>; 1716def : RWSysReg<"CNTPOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b110>; 1717def : RWSysReg<"CNTVFRQ_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b111>; 1718def : ROSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>; 1719def : ROSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>; 1720} 1721 1722// v8.7a LD64B/ST64B Accelerator Extension system register 1723let Requires = [{ {AArch64::FeatureLS64} }] in 1724def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>; 1725 1726// Branch Record Buffer system registers 1727let Requires = [{ {AArch64::FeatureBRBE} }] in { 1728def : RWSysReg<"BRBCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b000>; 1729def : RWSysReg<"BRBCR_EL12", 0b10, 0b101, 0b1001, 0b0000, 0b000>; 1730def : RWSysReg<"BRBCR_EL2", 0b10, 0b100, 0b1001, 0b0000, 0b000>; 1731def : RWSysReg<"BRBFCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b001>; 1732def : ROSysReg<"BRBIDR0_EL1", 0b10, 0b001, 0b1001, 0b0010, 0b000>; 1733def : RWSysReg<"BRBINFINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b000>; 1734def : RWSysReg<"BRBSRCINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b001>; 1735def : RWSysReg<"BRBTGTINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b010>; 1736def : RWSysReg<"BRBTS_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b010>; 1737foreach n = 0-31 in { 1738 defvar nb = !cast<bits<5>>(n); 1739 def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>; 1740 def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>; 1741 def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>; 1742} 1743} 1744 1745// Statistical Profiling Extension system register 1746let Requires = [{ {AArch64::FeatureSPE_EEF} }] in 1747def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>; 1748 1749// Cyclone specific system registers 1750// Op0 Op1 CRn CRm Op2 1751let Requires = [{ {AArch64::FeatureAppleA7SysReg} }] in 1752def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>; 1753 1754// Scalable Matrix Extension (SME) 1755// Op0 Op1 CRn CRm Op2 1756let Requires = [{ {AArch64::FeatureSME} }] in { 1757def : RWSysReg<"SMCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b110>; 1758def : RWSysReg<"SMCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b110>; 1759def : RWSysReg<"SMCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b110>; 1760def : RWSysReg<"SMCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b110>; 1761def : RWSysReg<"SVCR", 0b11, 0b011, 0b0100, 0b0010, 0b010>; 1762def : RWSysReg<"SMPRI_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b100>; 1763def : RWSysReg<"SMPRIMAP_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b101>; 1764def : ROSysReg<"SMIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b110>; 1765def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>; 1766} // HasSME 1767 1768// v8.4a MPAM and SME registers 1769// Op0 Op1 CRn CRm Op2 1770let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in { 1771def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>; 1772} // HasMPAM, HasSME 1773 1774// v8.8a Non-Maskable Interrupts 1775let Requires = [{ {AArch64::FeatureNMI} }] in { 1776 // Op0 Op1 CRn CRm Op2 1777 def : RWSysReg<"ALLINT", 0b11, 0b000, 0b0100, 0b0011, 0b000>; 1778 def : ROSysReg<"ICC_NMIAR1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI 1779} 1780 1781// v9.4a Guarded Control Stack Extension (GCS) 1782// Op0 Op1 CRn CRm Op2 1783def : RWSysReg<"GCSCR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b000>; 1784def : RWSysReg<"GCSPR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b001>; 1785def : RWSysReg<"GCSCRE0_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b010>; 1786def : RWSysReg<"GCSPR_EL0", 0b11, 0b011, 0b0010, 0b0101, 0b001>; 1787def : RWSysReg<"GCSCR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b000>; 1788def : RWSysReg<"GCSPR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b001>; 1789def : RWSysReg<"GCSCR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b000>; 1790def : RWSysReg<"GCSPR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b001>; 1791def : RWSysReg<"GCSCR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b000>; 1792def : RWSysReg<"GCSPR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b001>; 1793 1794// v8.9a/v9.4a Memory Attribute Index Enhancement (FEAT_AIE) 1795// Op0 Op1 CRn CRm Op2 1796def : RWSysReg<"AMAIR2_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b001>; 1797def : RWSysReg<"AMAIR2_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b001>; 1798def : RWSysReg<"AMAIR2_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b001>; 1799def : RWSysReg<"AMAIR2_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b001>; 1800def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>; 1801def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>; 1802def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>; 1803def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>; 1804 1805// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE) 1806// Op0 Op1 CRn CRm Op2 1807def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>; 1808def : RWSysReg<"PIRE0_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b010>; 1809def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>; 1810def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>; 1811def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>; 1812def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>; 1813def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>; 1814 1815// v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE) 1816// Op0 Op1 CRn CRm Op2 1817def : RWSysReg<"S2PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b101>; 1818 1819// v8.9a/v9.4a Stage 1 Permission Overlay Extension (FEAT_S1POE) 1820// Op0 Op1 CRn CRm Op2 1821def : RWSysReg<"POR_EL0", 0b11, 0b011, 0b1010, 0b0010, 0b100>; 1822def : RWSysReg<"POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b100>; 1823def : RWSysReg<"POR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b100>; 1824def : RWSysReg<"POR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b100>; 1825def : RWSysReg<"POR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b100>; 1826 1827// v8.9a/v9.4a Stage 2 Permission Overlay Extension (FEAT_S2POE) 1828// Op0 Op1 CRn CRm Op2 1829def : RWSysReg<"S2POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b101>; 1830 1831// v8.9a/v9.4a Extension to System Control Registers (FEAT_SCTLR2) 1832// Op0 Op1 CRn CRm Op2 1833def : RWSysReg<"SCTLR2_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b011>; 1834def : RWSysReg<"SCTLR2_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b011>; 1835def : RWSysReg<"SCTLR2_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b011>; 1836def : RWSysReg<"SCTLR2_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b011>; 1837 1838// v8.9a/v9.4a Extension to Translation Control Registers (FEAT_TCR2) 1839// Op0 Op1 CRn CRm Op2 1840def : RWSysReg<"TCR2_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b011>; 1841def : RWSysReg<"TCR2_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b011>; 1842def : RWSysReg<"TCR2_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b011>; 1843 1844// v8.9a/9.4a Translation Hardening Extension (FEAT_THE) 1845// Op0 Op1 CRn CRm Op2 1846let Requires = [{ {AArch64::FeatureTHE} }] in { 1847def : RWSysReg<"RCWMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b110>; 1848def : RWSysReg<"RCWSMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b011>; 1849} 1850 1851// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9) 1852// Op0 Op1 CRn CRm Op2 1853def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>; 1854 1855// v8.9a/9.4a new Performance Monitors Extension (FEAT_PMUv3p9) 1856// Op0 Op1 CRn CRm Op2 1857def : RWSysReg<"PMUACR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b100>; 1858 1859// v8.9a/9.4a PMU Snapshot Extension (FEAT_PMUv3_SS) 1860// Op0 Op1 CRn CRm Op2 1861def : ROSysReg<"PMCCNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1011, 0b111>; 1862def : ROSysReg<"PMICNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1100, 0b000>; 1863def : RWSysReg<"PMSSCR_EL1", 0b11, 0b000, 0b1001, 0b1101, 0b011>; 1864foreach n = 0-30 in { 1865 defvar nb = !cast<bits<5>>(n); 1866 def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b10, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>; 1867} 1868 1869// v8.9a/v9.4a PMUv3 Fixed-function instruction counter (FEAT_PMUv3_ICNTR) 1870// Op0 Op1 CRn CRm Op2 1871def : RWSysReg<"PMICNTR_EL0", 0b11, 0b011, 0b1001, 0b0100, 0b000>; 1872def : RWSysReg<"PMICFILTR_EL0", 0b11, 0b011, 0b1001, 0b0110, 0b000>; 1873 1874// v8.9a/v9.4a PMUv3 Performance Monitors Zero with Mask (FEAT_PMUv3p9/FEAT_PMUv3_ICNTR) 1875// Op0 Op1 CRn CRm Op2 1876def : WOSysReg<"PMZR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b100>; 1877 1878// v8.9a/9.4a Synchronous-Exception-Based Event Profiling extension (FEAT_SEBEP) 1879// Op0 Op1 CRn CRm Op2 1880def : RWSysReg<"PMECR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b101>; 1881def : RWSysReg<"PMIAR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b111>; 1882 1883// v8.9a/9.4a System Performance Monitors Extension (FEAT_SPMU) 1884// Op0 Op1 CRn CRm Op2 1885def : RWSysReg<"SPMACCESSR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b011>; 1886def : RWSysReg<"SPMACCESSR_EL12", 0b10, 0b101, 0b1001, 0b1101, 0b011>; 1887def : RWSysReg<"SPMACCESSR_EL2", 0b10, 0b100, 0b1001, 0b1101, 0b011>; 1888def : RWSysReg<"SPMACCESSR_EL3", 0b10, 0b110, 0b1001, 0b1101, 0b011>; 1889def : RWSysReg<"SPMCNTENCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b010>; 1890def : RWSysReg<"SPMCNTENSET_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b001>; 1891def : RWSysReg<"SPMCR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b000>; 1892def : ROSysReg<"SPMDEVAFF_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b110>; 1893def : ROSysReg<"SPMDEVARCH_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b101>; 1894foreach n = 0-15 in { 1895 defvar nb = !cast<bits<4>>(n); 1896 // Op0 Op1 CRn CRm Op2 1897 def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>; 1898 def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b10, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>; 1899 def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>; 1900 def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b10, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>; 1901} 1902// Op0 Op1 CRn CRm Op2 1903def : ROSysReg<"SPMIIDR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b100>; 1904def : RWSysReg<"SPMINTENCLR_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b010>; 1905def : RWSysReg<"SPMINTENSET_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b001>; 1906def : RWSysReg<"SPMOVSCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b011>; 1907def : RWSysReg<"SPMOVSSET_EL0", 0b10, 0b011, 0b1001, 0b1110, 0b011>; 1908def : RWSysReg<"SPMSELR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b101>; 1909def : ROSysReg<"SPMCGCR0_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b000>; 1910def : ROSysReg<"SPMCGCR1_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b001>; 1911def : ROSysReg<"SPMCFGR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b111>; 1912def : RWSysReg<"SPMROOTCR_EL3", 0b10, 0b110, 0b1001, 0b1110, 0b111>; 1913def : RWSysReg<"SPMSCR_EL1", 0b10, 0b111, 0b1001, 0b1110, 0b111>; 1914 1915// v8.9a/9.4a Instrumentation Extension (FEAT_ITE) 1916// Op0 Op1 CRn CRm Op2 1917let Requires = [{ {AArch64::FeatureITE} }] in { 1918def : RWSysReg<"TRCITEEDCR", 0b10, 0b001, 0b0000, 0b0010, 0b001>; 1919def : RWSysReg<"TRCITECR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b011>; 1920def : RWSysReg<"TRCITECR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b011>; 1921def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>; 1922} 1923 1924// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS) 1925// Op0 Op1 CRn CRm Op2 1926def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>; 1927 1928// v8.9a/9.4a RASv2 (FEAT_RASv2) 1929// Op0 Op1 CRn CRm Op2 1930let Requires = [{ {AArch64::FeatureRASv2} }] in 1931def : ROSysReg<"ERXGSR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b010>; 1932 1933// v8.9a/9.4a Physical Fault Address (FEAT_PFAR) 1934// Op0 Op1 CRn CRm Op2 1935def : RWSysReg<"PFAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b101>; 1936def : RWSysReg<"PFAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b101>; 1937def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>; 1938 1939// v9.4a Exception-based event profiling (FEAT_EBEP) 1940// Op0 Op1 CRn CRm Op2 1941def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>; 1942 1943// 2023 ISA Extension 1944// AArch64 Floating-point Mode Register controls behaviors of the FP8 1945// instructions (FEAT_FPMR) 1946// Op0 Op1 CRn CRm Op2 1947def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>; 1948def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>; 1949 1950// v9.5a Software Stepping Enhancements (FEAT_STEP2) 1951// Op0 Op1 CRn CRm Op2 1952def : RWSysReg<"MDSTEPOP_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b010>; 1953 1954// v9.5a System PMU zero register (FEAT_SPMU2) 1955// Op0 Op1 CRn CRm Op2 1956def : WOSysReg<"SPMZR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b100>; 1957 1958// v9.5a Delegated SError exceptions for EL3 (FEAT_E3DSE) 1959// Op0 Op1 CRn CRm Op2 1960def : RWSysReg<"VDISR_EL3", 0b11, 0b110, 0b1100, 0b0001, 0b001>; 1961def : RWSysReg<"VSESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b011>; 1962 1963// v9.5a Hardware Dirty State Tracking Structure (FEAT_HDBSS) 1964// Op0 Op1 CRn CRm Op2 1965def : RWSysReg<"HDBSSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b010>; 1966def : RWSysReg<"HDBSSPROD_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b011>; 1967 1968// v9.5a Hardware Accelerator for Cleaning Dirty State (FEAT_HACDBS) 1969// Op0 Op1 CRn CRm Op2 1970def : RWSysReg<"HACDBSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b100>; 1971def : RWSysReg<"HACDBSCONS_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b101>; 1972 1973// v9.5a Fine Grained Write Trap EL3 (FEAT_FGWTE3) 1974// Op0 Op1 CRn CRm Op2 1975def : RWSysReg<"FGWTE3_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b101>; 1976