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Searched refs:MIB (Results 1 – 25 of 238) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h108 MachineInstrBuilder MIB = variable
110 MIB.add(MI->getOperand(1));
111 MIB.addImm(0);
112 MIB.addImm(ARMCC::AL);
113 MIB.addReg(ARM::NoRegister);
115 MachineInstrBuilder MIB = variable
117 MIB.add(MI->getOperand(0));
118 MIB.add(MI->getOperand(1));
119 MIB.addImm(0);
120 MIB.addImm(ARMCC::AL);
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H A DARMInstructionSelector.cpp47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
145 void renderInvertedImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
233 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
242 Register VReg0 = MIB.getReg(0); in selectMergeValues()
247 Register VReg1 = MIB.getReg(1); in selectMergeValues()
252 Register VReg2 = MIB.getReg(2); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
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H A DARMExpandPseudoInsts.cpp562 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
590 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
594 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
596 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
598 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
600 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
604 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
607 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
608 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
635 MIB.add(AM6Offset); in ExpandVLD()
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H A DThumb2SizeReduction.cpp478 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1)) in ReduceLoadStore() local
486 MIB.setMemRefs(MI->memoperands()); in ReduceLoadStore()
489 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
590 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local
595 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead); in ReduceLoadStore()
598 MIB.add(MI->getOperand(0)); in ReduceLoadStore()
599 MIB.add(MI->getOperand(1)); in ReduceLoadStore()
602 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
607 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
613 MIB.add(MO); in ReduceLoadStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp75 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in INITIALIZE_PASS() local
84 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
86 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
88 return TII->ExpandMOVI(MIB, MVT::i32); in INITIALIZE_PASS()
91 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
93 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
95 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
98 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
100 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
102 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
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H A DM68kInstrInfo.cpp351 bool M68kInstrInfo::ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const { in ExpandMOVI() argument
352 Register Reg = MIB->getOperand(0).getReg(); in ExpandMOVI()
353 int64_t Imm = MIB->getOperand(1).getImm(); in ExpandMOVI()
363 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVI()
373 MIB->setDesc(get(M68k::MOVQ)); in ExpandMOVI()
374 MIB->getOperand(0).setReg(SReg); in ExpandMOVI()
377 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri)); in ExpandMOVI()
383 bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, in ExpandMOVX_RR() argument
386 Register Dst = MIB->getOperand(0).getReg(); in ExpandMOVX_RR()
387 Register Src = MIB->getOperand(1).getReg(); in ExpandMOVX_RR()
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H A DM68kInstrBuilder.h41 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
42 return MIB.addImm(Offset); in addOffset()
49 addRegIndirectWithDisp(const MachineInstrBuilder &MIB, Register Reg, in addRegIndirectWithDisp() argument
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill)); in addRegIndirectWithDisp()
59 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
60 MachineInstr *MI = MIB;
72 return MIB.addImm(Offset).addFrameIndex(FI).addMemOperand(MMO);
76 addMemOperand(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
77 MachineInstr *MI = MIB;
89 return MIB.addMemOperand(MMO);
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp61 void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB,
64 bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB,
69 bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB,
71 bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
72 bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB,
75 bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
76 bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB,
78 bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
81 MachineIRBuilder &MIB) const;
82 bool selectMergeValues(MachineInstr &MI, MachineIRBuilder &MIB,
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H A DRISCVLegalizerInfo.cpp587 MachineIRBuilder &MIB) const { in legalizeVScale()
605 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
606 MIB.buildLShr(Dst, VLENB, MIB.buildConstant(XLenTy, 3 - Log2)); in legalizeVScale()
608 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
609 MIB.buildShl(Dst, VLENB, MIB.buildConstant(XLenTy, Log2 - 3)); in legalizeVScale()
611 MIB.buildInstr(RISCV::G_READ_VLENB, {Dst}, {}); in legalizeVScale()
616 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
617 MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8)); in legalizeVScale()
619 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
620 auto VScale = MIB.buildLShr(XLenTy, VLENB, MIB.buildConstant(XLenTy, 3)); in legalizeVScale()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
143 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
157 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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H A DX86CallLowering.cpp
H A DX86FixupBWInsts.cpp288 MachineInstrBuilder MIB = in tryReplaceLoad() local
293 MIB.add(MI->getOperand(i)); in tryReplaceLoad()
295 MIB.setMemRefs(MI->memoperands()); in tryReplaceLoad()
299 unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(), in tryReplaceLoad()
301 unsigned NewInstrNum = MIB->getDebugInstrNum(*MF); in tryReplaceLoad()
305 return MIB; in tryReplaceLoad()
332 MachineInstrBuilder MIB = in tryReplaceCopy() local
340 MIB.add(Op); in tryReplaceCopy()
342 return MIB; in tryReplaceCopy()
360 MachineInstrBuilder MIB = in tryReplaceExtend() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp557 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
562 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
702 auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) in selectG_BUILD_VECTOR() local
705 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
708 MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) in selectG_BUILD_VECTOR()
712 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
753 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR() local
759 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR()
861 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp187 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
225 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
238 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
250 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
317 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
329 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
381 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
383 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
384 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
391 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp45 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { in insertInstr() argument
46 getMBB().insert(getInsertPt(), MIB); in insertInstr()
47 recordInsertion(MIB); in insertInstr()
48 return MIB; in insertInstr()
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); in buildConstDbgValue() local
111 MIB.addCImm(CI); in buildConstDbgValue()
113 MIB.addImm(CI->getZExtValue()); in buildConstDbgValue()
115 MIB.addFPImm(CFP); in buildConstDbgValue()
117 MIB.addImm(0); in buildConstDbgValue()
120 MIB.addReg(Register()); in buildConstDbgValue()
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H A DCSEMIRBuilder.cpp128 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB, in memoizeMI() argument
130 assert(canPerformCSEForOpc(MIB->getOpcode()) && in memoizeMI()
132 MachineInstr *MIBInstr = MIB; in memoizeMI()
134 return MIB; in memoizeMI()
149 MachineInstrBuilder &MIB) { in generateCopiesIfRequired() argument
155 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
165 Observer->changingInstr(*MIB); in generateCopiesIfRequired()
166 MIB->setDebugLoc( in generateCopiesIfRequired()
167 DILocation::getMergedLocation(MIB->getDebugLoc(), getDebugLoc())); in generateCopiesIfRequired()
169 Observer->changedInstr(*MIB); in generateCopiesIfRequired()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp92 MachineIRBuilder MIB(MF); in addConstantsToTrack() local
94 GR->getOrCreateSPIRVType(Const->getType(), MIB); in addConstantsToTrack()
169 MachineIRBuilder MIB) { in insertBitcasts() argument
172 static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget()); in insertBitcasts()
180 MIB.setInsertPt(*MI.getParent(), MI); in insertBitcasts()
183 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
189 SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElemTy, MIB); in insertBitcasts()
198 if (MachineInstr *AssignMI = findAssignTypeInstr(Def, MIB.getMRI())) in insertBitcasts()
200 MIB.getMRI()->replaceRegWith(Def, Source); in insertBitcasts()
203 MIB.buildBitcast(Def, Source); in insertBitcasts()
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H A DSPIRVUtils.cpp59 void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB) { in addStringImm() argument
63 MIB.addImm(convertCharsToWord(Str, i)); in addStringImm()
80 void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) { in addNumImm() argument
85 MIB.addImm(Imm.getZExtValue()); in addNumImm()
88 MIB.getInstr()->setAsmPrinterFlag(SPIRV::ASM_PRINTER_WIDTH16); in addNumImm()
94 MIB.addImm(LowBits).addImm(HighBits); in addNumImm()
103 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); in buildOpName() local
104 addStringImm(Name, MIB); in buildOpName()
108 static void finishBuildOpDecorate(MachineInstrBuilder &MIB, in finishBuildOpDecorate() argument
112 addStringImm(StrImm, MIB); in finishBuildOpDecorate()
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H A DSPIRVGlobalRegistry.cpp124 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt) in getOpTypeInt() local
128 return MIB; in getOpTypeInt()
133 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat) in getOpTypeFloat() local
136 return MIB; in getOpTypeFloat()
153 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeVector) in getOpTypeVector() local
157 return MIB; in getOpTypeVector()
243 MachineInstrBuilder MIB; in getOrCreateConstFP() local
247 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) in getOrCreateConstFP()
251 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantF)) in getOrCreateConstFP()
256 MIB); in getOrCreateConstFP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp37 MachineInstrBuilder &MIB) in CallReturnHandler()
38 : M68kIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
44 MachineInstrBuilder &MIB; member
54 MachineInstrBuilder MIB) in M68kOutgoingArgHandler()
55 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), in M68kOutgoingArgHandler()
61 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
89 MachineInstrBuilder MIB; member
98 auto MIB = MIRBuilder.buildInstrNoInsert(M68k::RTS); in lowerReturn() local
113 M68kOutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB); in lowerReturn()
118 MIRBuilder.insertInstr(MIB); in lowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp83 MIB.setMF(MF); in setupMF()
130 MachineIRBuilder &MIB) const;
132 MachineIRBuilder &MIB) const;
134 MachineIRBuilder &MIB) const;
137 MachineIRBuilder &MIB) const;
351 MachineIRBuilder &MIB) const;
356 MachineIRBuilder &MIB) const;
360 MachineIRBuilder &MIB) const;
367 MachineIRBuilder &MIB) const;
372 MachineIRBuilder &MIB) const;
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H A DAArch64CallLowering.cpp225 MachineInstrBuilder MIB) in CallReturnHandler()
226 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
229 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
232 MachineInstrBuilder MIB; member
239 MachineInstrBuilder MIB) in ReturnedArgCallReturnHandler()
240 : CallReturnHandler(MIRBuilder, MRI, MIB) {} in ReturnedArgCallReturnHandler()
247 MachineInstrBuilder MIB, bool IsTailCall = false, in OutgoingArgHandler()
249 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall), in OutgoingArgHandler()
294 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
337 MachineInstrBuilder MIB; member
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp88 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) in X86OutgoingValueHandler()
89 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), in X86OutgoingValueHandler()
111 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
128 MachineInstrBuilder &MIB; member
150 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn() local
158 MIB.addReg(RetReg); in lowerReturn()
161 MIB.addReg(RetReg); in lowerReturn()
174 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB); in lowerReturn()
181 MIRBuilder.insertInstr(MIB); in lowerReturn()
247 MachineInstrBuilder &MIB) in CallReturnHandler()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp570 MachineInstrBuilder MIB; in changeLoad() local
576 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
577 MIB.add(OldMI->getOperand(0)); in changeLoad()
578 MIB.add(OldMI->getOperand(2)); in changeLoad()
579 MIB.add(OldMI->getOperand(3)); in changeLoad()
580 MIB.add(ImmOp); in changeLoad()
587 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
592 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
599 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); in changeLoad()
604 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DMemoryProfileInfo.cpp80 MDNode *llvm::memprof::getMIBStackNode(const MDNode *MIB) { in getMIBStackNode() argument
81 assert(MIB->getNumOperands() >= 2); in getMIBStackNode()
83 return cast<MDNode>(MIB->getOperand(0)); in getMIBStackNode()
86 AllocationType llvm::memprof::getMIBAllocType(const MDNode *MIB) { in getMIBAllocType() argument
87 assert(MIB->getNumOperands() >= 2); in getMIBAllocType()
91 auto *MDS = dyn_cast<MDString>(MIB->getOperand(1)); in getMIBAllocType()
101 uint64_t llvm::memprof::getMIBTotalSize(const MDNode *MIB) { in getMIBTotalSize() argument
102 if (MIB->getNumOperands() < 3) in getMIBTotalSize()
104 return mdconst::dyn_extract<ConstantInt>(MIB->getOperand(2))->getZExtValue(); in getMIBTotalSize()
173 void CallStackTrie::addCallStack(MDNode *MIB) { in addCallStack() argument
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