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Searched refs:MIB (Results 1 – 25 of 243) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h108 MachineInstrBuilder MIB = variable
110 MIB.add(MI->getOperand(1));
111 MIB.addImm(0);
112 MIB.addImm(ARMCC::AL);
113 MIB.addReg(ARM::NoRegister);
115 MachineInstrBuilder MIB = variable
117 MIB.add(MI->getOperand(0));
118 MIB.add(MI->getOperand(1));
119 MIB.addImm(0);
120 MIB.addImm(ARMCC::AL);
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H A DARMInstructionSelector.cpp47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
145 void renderInvertedImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
233 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
242 Register VReg0 = MIB.getReg(0); in selectMergeValues()
247 Register VReg1 = MIB.getReg(1); in selectMergeValues()
252 Register VReg2 = MIB.getReg(2); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
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H A DARMExpandPseudoInsts.cpp561 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
589 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
593 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
595 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
597 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
599 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
603 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
606 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
607 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
634 MIB.add(AM6Offset); in ExpandVLD()
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H A DThumb2SizeReduction.cpp475 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1)) in ReduceLoadStore() local
483 MIB.setMemRefs(MI->memoperands()); in ReduceLoadStore()
486 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
587 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local
592 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead); in ReduceLoadStore()
595 MIB.add(MI->getOperand(0)); in ReduceLoadStore()
596 MIB.add(MI->getOperand(1)); in ReduceLoadStore()
599 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
604 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
610 MIB.add(MO); in ReduceLoadStore()
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H A DARMCallLowering.cpp98 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) in ARMOutgoingValueHandler()
99 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in ARMOutgoingValueHandler()
129 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
183 MachineInstrBuilder MIB; member
434 MachineInstrBuilder MIB) in CallReturnHandler()
435 : ARMIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
438 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
441 MachineInstrBuilder MIB; member
483 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); in lowerCall() local
487 MIB.add(predOps(ARMCC::AL)); in lowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp74 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in INITIALIZE_PASS() local
83 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
85 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
87 return TII->ExpandMOVI(MIB, MVT::i32); in INITIALIZE_PASS()
90 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
92 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
94 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
97 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
99 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
101 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
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H A DM68kInstrInfo.cpp353 bool M68kInstrInfo::ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const { in ExpandMOVI() argument
354 Register Reg = MIB->getOperand(0).getReg(); in ExpandMOVI()
355 int64_t Imm = MIB->getOperand(1).getImm(); in ExpandMOVI()
372 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVI()
378 MIB->setDesc(get(M68k::MOVQ)); in ExpandMOVI()
379 MIB->getOperand(0).setReg(SReg); in ExpandMOVI()
386 MachineBasicBlock &MBB = *MIB->getParent(); in ExpandMOVI()
387 DebugLoc DL = MIB->getDebugLoc(); in ExpandMOVI()
392 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::MOVQ), SReg).addImm(~Imm & 0xFF); in ExpandMOVI()
393 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::NOT8d), SubReg).addReg(SubReg); in ExpandMOVI()
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H A DM68kInstrBuilder.h41 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
42 return MIB.addImm(Offset); in addOffset()
49 addRegIndirectWithDisp(const MachineInstrBuilder &MIB, Register Reg, in addRegIndirectWithDisp() argument
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill)); in addRegIndirectWithDisp()
59 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
60 MachineInstr *MI = MIB;
72 return MIB.addImm(Offset).addFrameIndex(FI).addMemOperand(MMO);
76 addMemOperand(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
77 MachineInstr *MI = MIB;
89 return MIB.addMemOperand(MMO);
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp80 void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB);
82 bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB);
86 bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB) const;
87 bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
88 bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB, bool IsLocal = true,
90 bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB) const;
91 bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB) const;
93 MachineIRBuilder &MIB) const;
94 bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB) const;
134 void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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H A DRISCVLegalizerInfo.cpp842 MachineIRBuilder &MIB) const { in legalizeVScale()
860 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
861 MIB.buildLShr(Dst, VLENB, MIB.buildConstant(XLenTy, 3 - Log2)); in legalizeVScale()
863 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
864 MIB.buildShl(Dst, VLENB, MIB.buildConstant(XLenTy, Log2 - 3)); in legalizeVScale()
866 MIB.buildInstr(RISCV::G_READ_VLENB, {Dst}, {}); in legalizeVScale()
871 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
872 MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8)); in legalizeVScale()
874 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
875 auto VScale = MIB.buildLShr(XLenTy, VLENB, MIB.buildConstant(XLenTy, 3)); in legalizeVScale()
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H A DRISCVLegalizerInfo.h47 bool legalizeVScale(MachineInstr &MI, MachineIRBuilder &MIB) const;
49 bool legalizeSplatVector(MachineInstr &MI, MachineIRBuilder &MIB) const;
50 bool legalizeExtractSubvector(MachineInstr &MI, MachineIRBuilder &MIB) const;
52 MachineIRBuilder &MIB) const;
54 MachineIRBuilder &MIB) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h118 addDirectMem(const MachineInstrBuilder &MIB, Register Reg) { in addDirectMem() argument
121 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
137 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
138 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
142 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
143 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
151 addRegOffset(const MachineInstrBuilder &MIB, Register Reg, bool isKill, in addRegOffset() argument
153 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
159 addRegReg(const MachineInstrBuilder &MIB, Register Reg1, bool isKill1, in addRegReg() argument
161 return MIB.addReg(Reg1, getKillRegState(isKill1), SubReg1) in addRegReg()
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H A DX86FixupBWInsts.cpp287 MachineInstrBuilder MIB = in tryReplaceLoad() local
292 MIB.add(MI->getOperand(i)); in tryReplaceLoad()
294 MIB.setMemRefs(MI->memoperands()); in tryReplaceLoad()
298 unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(), in tryReplaceLoad()
300 unsigned NewInstrNum = MIB->getDebugInstrNum(*MF); in tryReplaceLoad()
304 return MIB; in tryReplaceLoad()
331 MachineInstrBuilder MIB = in tryReplaceCopy() local
339 MIB.add(Op); in tryReplaceCopy()
341 return MIB; in tryReplaceCopy()
359 MachineInstrBuilder MIB = in tryReplaceExtend() local
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H A DX86CallLowering.cpp
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp186 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
224 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
237 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
249 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
315 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
327 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
354 BuildMI(*MBB, InsertPos, MIB->getDebugLoc(), in AddRegisterOperand()
380 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
382 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
383 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp655 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
659 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
660 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
800 auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) in selectG_BUILD_VECTOR() local
803 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
806 MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) in selectG_BUILD_VECTOR()
810 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
851 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR() local
857 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR()
959 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX() local
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H A DAMDGPUInstructionSelector.h332 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
335 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
337 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
340 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
343 void renderSrcAndDstSelToOpSelXForm_0_0(MachineInstrBuilder &MIB,
347 void renderSrcAndDstSelToOpSelXForm_0_1(MachineInstrBuilder &MIB,
351 void renderSrcAndDstSelToOpSelXForm_1_0(MachineInstrBuilder &MIB,
355 void renderSrcAndDstSelToOpSelXForm_1_1(MachineInstrBuilder &MIB,
359 void renderDstSelToOpSelXForm(MachineInstrBuilder &MIB,
362 void renderSrcSelToOpSelXForm(MachineInstrBuilder &MIB,
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp98 MachineIRBuilder MIB(DepMBB, DepMBB.getFirstNonPHI()); in addConstantsToTrack() local
100 Const->getType(), MIB, SPIRV::AccessQualifier::ReadWrite, in addConstantsToTrack()
139 MachineIRBuilder MIB) { in foldConstantsIntoIntrinsics() argument
148 MIB.setInsertPt(*MI.getParent(), MI); in foldConstantsIntoIntrinsics()
149 buildOpName(MI.getOperand(1).getReg(), ValueName, MIB); in foldConstantsIntoIntrinsics()
175 static void buildOpBitcast(SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, in buildOpBitcast() argument
182 MachineRegisterInfo *MRI = MIB.getMRI(); in buildOpBitcast()
186 MIB.buildInstr(TargetOpcode::COPY).addDef(ResVReg).addUse(OpReg); in buildOpBitcast()
188 MIB.buildInstr(SPIRV::OpBitcast) in buildOpBitcast()
213 MachineIRBuilder MIB) { in selectOpBitcasts() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp45 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { in insertInstr() argument
46 getMBB().insert(getInsertPt(), MIB); in insertInstr()
47 recordInsertion(MIB); in insertInstr()
48 return MIB; in insertInstr()
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); in buildConstDbgValue() local
111 MIB.addCImm(CI); in buildConstDbgValue()
113 MIB.addImm(CI->getZExtValue()); in buildConstDbgValue()
115 MIB.addFPImm(CFP); in buildConstDbgValue()
117 MIB.addImm(0); in buildConstDbgValue()
120 MIB.addReg(Register()); in buildConstDbgValue()
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H A DCSEMIRBuilder.cpp132 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB, in memoizeMI() argument
134 assert(canPerformCSEForOpc(MIB->getOpcode()) && in memoizeMI()
136 MachineInstr *MIBInstr = MIB; in memoizeMI()
138 return MIB; in memoizeMI()
153 MachineInstrBuilder &MIB) { in generateCopiesIfRequired() argument
159 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
169 Observer->changingInstr(*MIB); in generateCopiesIfRequired()
170 MIB->setDebugLoc( in generateCopiesIfRequired()
171 DebugLoc::getMergedLocation(MIB->getDebugLoc(), getDebugLoc())); in generateCopiesIfRequired()
173 Observer->changedInstr(*MIB); in generateCopiesIfRequired()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp37 MachineInstrBuilder &MIB) in CallReturnHandler()
38 : M68kIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
44 MachineInstrBuilder &MIB; member
54 MachineInstrBuilder MIB) in M68kOutgoingArgHandler()
55 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), in M68kOutgoingArgHandler()
61 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
89 MachineInstrBuilder MIB; member
98 auto MIB = MIRBuilder.buildInstrNoInsert(M68k::RTS); in lowerReturn() local
113 M68kOutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB); in lowerReturn()
118 MIRBuilder.insertInstr(MIB); in lowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp83 MIB.setMF(MF); in setupMF()
130 MachineIRBuilder &MIB) const;
132 MachineIRBuilder &MIB) const;
134 MachineIRBuilder &MIB) const;
137 MachineIRBuilder &MIB) const;
351 MachineIRBuilder &MIB) const;
356 MachineIRBuilder &MIB) const;
360 MachineIRBuilder &MIB) const;
367 MachineIRBuilder &MIB) const;
372 MachineIRBuilder &MIB) const;
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H A DAArch64CallLowering.cpp227 MachineInstrBuilder MIB) in CallReturnHandler()
228 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
231 MIB.addDef(Reg, RegState::Implicit); in markRegUsed()
234 MachineInstrBuilder MIB; member
241 MachineInstrBuilder MIB) in ReturnedArgCallReturnHandler()
242 : CallReturnHandler(MIRBuilder, MRI, MIB) {} in ReturnedArgCallReturnHandler()
249 MachineInstrBuilder MIB, bool IsTailCall = false, in OutgoingArgHandler()
251 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall), in OutgoingArgHandler()
296 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
386 MachineInstrBuilder MIB; member
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp87 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) in X86OutgoingValueHandler()
88 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), in X86OutgoingValueHandler()
110 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
127 MachineInstrBuilder &MIB; member
149 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn() local
157 MIB.addReg(RetReg); in lowerReturn()
160 MIB.addReg(RetReg); in lowerReturn()
173 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB); in lowerReturn()
180 MIRBuilder.insertInstr(MIB); in lowerReturn()
246 MachineInstrBuilder &MIB) in CallReturnHandler()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp852 MachineInstrBuilder MIB; in changeLoad() local
858 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
859 MIB.add(OldMI->getOperand(0)); in changeLoad()
860 MIB.add(OldMI->getOperand(2)); in changeLoad()
861 MIB.add(OldMI->getOperand(3)); in changeLoad()
862 MIB.add(ImmOp); in changeLoad()
869 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
874 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
881 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); in changeLoad()
886 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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