Lines Matching refs:MIB
557 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
562 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
702 auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) in selectG_BUILD_VECTOR() local
705 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
708 MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) in selectG_BUILD_VECTOR()
712 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
753 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR() local
759 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR()
861 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX() local
866 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_SBFX_UBFX()
931 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_WRITELANE_B32), VDst); in selectWritelane() local
938 MIB.addReg(Val); in selectWritelane()
939 MIB.addImm(ConstSelect->Value.getSExtValue() & in selectWritelane()
949 MIB.addImm(ConstVal->Value.getSExtValue()); in selectWritelane()
950 MIB.addReg(LaneSelect); in selectWritelane()
952 MIB.addReg(Val); in selectWritelane()
959 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectWritelane()
961 MIB.addReg(AMDGPU::M0); in selectWritelane()
965 MIB.addReg(VDstIn); in selectWritelane()
968 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectWritelane()
997 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0) in selectDivScale() local
1009 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDivScale()
1485 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg); in selectGroupStaticSize() local
1489 MIB.addImm(MFI->getLDSSize()); in selectGroupStaticSize()
1494 MIB.addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO); in selectGroupStaticSize()
1498 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGroupStaticSize()
1709 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID))); in selectDSGWSIntrinsic() local
1713 MIB.addReg(VSrc); in selectDSGWSIntrinsic()
1719 MIB.addImm(ImmOffset) in selectDSGWSIntrinsic()
1722 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::data0); in selectDSGWSIntrinsic()
1752 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg()) in selectDSAppendConsume() local
1757 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDSAppendConsume()
1970 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opcode)) in selectImageIntrinsic() local
1981 MIB.addDef(TmpReg); in selectImageIntrinsic()
1988 MIB.addDef(VDataOut); // vdata output in selectImageIntrinsic()
1993 MIB.addReg(VDataIn); // vdata input in selectImageIntrinsic()
1999 MIB.addReg(SrcOp.getReg()); in selectImageIntrinsic()
2003 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
2005 MIB.addReg(MI.getOperand(ArgOffset + Intr->SampIndex).getReg()); in selectImageIntrinsic()
2007 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
2010 MIB.addImm(DimInfo->Encoding); in selectImageIntrinsic()
2012 MIB.addImm(Unorm); in selectImageIntrinsic()
2014 MIB.addImm(CPol); in selectImageIntrinsic()
2015 MIB.addImm(IsA16 && // a16 or r128 in selectImageIntrinsic()
2018 MIB.addImm(IsA16 ? -1 : 0); in selectImageIntrinsic()
2021 MIB.addImm(TFE); // tfe in selectImageIntrinsic()
2028 MIB.addImm(LWE); // lwe in selectImageIntrinsic()
2030 MIB.addImm(DimInfo->DA ? -1 : 0); in selectImageIntrinsic()
2032 MIB.addImm(IsD16 ? -1 : 0); in selectImageIntrinsic()
2035 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectImageIntrinsic()
2036 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::vaddr); in selectImageIntrinsic()
2055 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::DS_BVH_STACK_RTN_B32), Dst0) in selectDSBvhStackIntrinsic() local
2064 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDSBvhStackIntrinsic()
2923 auto MIB = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_AND_B64), DstReg) in selectG_PTRMASK() local
2928 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_PTRMASK()
3232 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc)); in selectBufferLoadLds() local
3236 BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), IdxReg) in selectBufferLoadLds()
3242 MIB.addReg(IdxReg); in selectBufferLoadLds()
3244 MIB.addReg(VIndex); in selectBufferLoadLds()
3246 MIB.addReg(VOffset); in selectBufferLoadLds()
3249 MIB.add(MI.getOperand(1)); // rsrc in selectBufferLoadLds()
3250 MIB.add(MI.getOperand(5 + OpOffset)); // soffset in selectBufferLoadLds()
3251 MIB.add(MI.getOperand(6 + OpOffset)); // imm offset in selectBufferLoadLds()
3253 MIB.addImm(Aux & AMDGPU::CPol::ALL); // cpol in selectBufferLoadLds()
3254 MIB.addImm(Aux & AMDGPU::CPol::SWZ_pregfx12 ? 1 : 0); // swz in selectBufferLoadLds()
3272 MIB.setMemRefs({LoadMMO, StoreMMO}); in selectBufferLoadLds()
3275 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectBufferLoadLds()
3351 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc)) in selectGlobalLoadLds() local
3355 MIB.addReg(VOffset); in selectGlobalLoadLds()
3357 MIB.add(MI.getOperand(4)) // offset in selectGlobalLoadLds()
3374 MIB.setMemRefs({LoadMMO, StoreMMO}); in selectGlobalLoadLds()
3377 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobalLoadLds()
3652 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
3716 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
3727 [=](MachineInstrBuilder &MIB) { in selectVOP3Mods0()
3728 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods0()
3730 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3Mods0()
3731 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3Mods0()
3732 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3Mods0()
3745 [=](MachineInstrBuilder &MIB) { in selectVOP3BMods0()
3746 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods0()
3748 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVOP3BMods0()
3749 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3BMods0()
3750 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3BMods0()
3757 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, in selectVOP3OMods()
3758 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp in selectVOP3OMods()
3759 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod in selectVOP3OMods()
3770 [=](MachineInstrBuilder &MIB) { in selectVOP3Mods()
3771 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3Mods()
3773 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3Mods()
3785 [=](MachineInstrBuilder &MIB) { in selectVOP3ModsNonCanonicalizing()
3786 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3ModsNonCanonicalizing()
3788 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3ModsNonCanonicalizing()
3800 [=](MachineInstrBuilder &MIB) { in selectVOP3BMods()
3801 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB)); in selectVOP3BMods()
3803 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3BMods()
3814 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectVOP3NoMods()
3854 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMods()
3855 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMods()
3869 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PModsDOT()
3870 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PModsDOT()
3885 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PModsNeg()
3899 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectWMMAOpSelVOP3PMods()
3922 auto MIB = B.buildInstr(AMDGPU::REG_SEQUENCE) in buildRegSequence() local
3925 MIB.addReg(Elts[i]); in buildRegSequence()
3926 MIB.addImm(SIRegisterInfo::getSubRegFromChannel(i)); in buildRegSequence()
3928 return MIB->getOperand(0).getReg(); in buildRegSequence()
3988 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF32NegAbs()
3989 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF32NegAbs()
4014 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16Neg()
4015 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF16Neg()
4047 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectWMMAModsF16NegAbs()
4048 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}}; in selectWMMAModsF16NegAbs()
4056 return {{[=](MachineInstrBuilder &MIB) { in selectWMMAVISrc()
4057 MIB.addImm(FPValReg->Value.bitcastToAPInt().getSExtValue()); in selectWMMAVISrc()
4069 {[=](MachineInstrBuilder &MIB) { MIB.addImm(ICst.getSExtValue()); }}}; in selectWMMAVISrc()
4092 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex8()
4093 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key in selectSWMMACIndex8()
4114 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectSWMMACIndex16()
4115 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key in selectSWMMACIndex16()
4127 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3OpSelMods()
4128 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3OpSelMods()
4142 [=](MachineInstrBuilder &MIB) { in selectVINTERPMods()
4143 MIB.addReg( in selectVINTERPMods()
4144 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true)); in selectVINTERPMods()
4146 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPMods()
4160 [=](MachineInstrBuilder &MIB) { in selectVINTERPModsHi()
4161 MIB.addReg( in selectVINTERPModsHi()
4162 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true)); in selectVINTERPModsHi()
4164 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods in selectVINTERPModsHi()
4256 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdImm()
4257 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdImm()
4276 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
4277 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } in selectSmrdImm32()
4287 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgpr()
4288 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectSmrdSgpr()
4298 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); }, in selectSmrdSgprImm()
4299 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSmrdSgprImm()
4300 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}}; in selectSmrdSgprImm()
4334 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectFlatOffset()
4335 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectFlatOffset()
4344 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectGlobalOffset()
4345 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectGlobalOffset()
4354 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); }, in selectScratchOffset()
4355 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); }, in selectScratchOffset()
4400 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr in selectGlobalSAddr()
4401 [=](MachineInstrBuilder &MIB) { in selectGlobalSAddr()
4402 MIB.addReg(HighBits); in selectGlobalSAddr()
4404 [=](MachineInstrBuilder &MIB) { MIB.addImm(SplitImmOffset); }, in selectGlobalSAddr()
4436 return {{[=](MachineInstrBuilder &MIB) { // saddr in selectGlobalSAddr()
4437 MIB.addReg(SAddr); in selectGlobalSAddr()
4439 [=](MachineInstrBuilder &MIB) { // voffset in selectGlobalSAddr()
4440 MIB.addReg(VOffset); in selectGlobalSAddr()
4442 [=](MachineInstrBuilder &MIB) { // offset in selectGlobalSAddr()
4443 MIB.addImm(ImmOffset); in selectGlobalSAddr()
4465 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()
4466 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
4467 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectGlobalSAddr()
4493 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr in selectScratchSAddr()
4494 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
4525 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr in selectScratchSAddr()
4526 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSAddr()
4591 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4592 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr in selectScratchSVAddr()
4593 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
4601 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr in selectScratchSVAddr()
4602 [=](MachineInstrBuilder &MIB) { MIB.addReg(LHS); }, // saddr in selectScratchSVAddr()
4603 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectScratchSVAddr()
4626 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
4627 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4629 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
4630 MIB.addReg(HighBits); in selectMUBUFScratchOffen()
4632 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
4635 MIB.addImm(0); in selectMUBUFScratchOffen()
4637 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
4638 MIB.addImm(Offset & MaxOffset); in selectMUBUFScratchOffen()
4668 return {{[=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffen()
4669 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffen()
4671 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFScratchOffen()
4673 MIB.addFrameIndex(*FI); in selectMUBUFScratchOffen()
4675 MIB.addReg(VAddr); in selectMUBUFScratchOffen()
4677 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffen()
4680 MIB.addImm(0); in selectMUBUFScratchOffen()
4682 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFScratchOffen()
4683 MIB.addImm(Offset); in selectMUBUFScratchOffen()
4834 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4835 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4837 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4838 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4840 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // offset in selectMUBUFScratchOffset()
4859 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4860 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4862 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4863 MIB.addReg(WaveBase); in selectMUBUFScratchOffset()
4865 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
4874 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFScratchOffset()
4875 MIB.addReg(Info->getScratchRSrcReg()); in selectMUBUFScratchOffset()
4877 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFScratchOffset()
4878 MIB.addImm(0); in selectMUBUFScratchOffset()
4880 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset in selectMUBUFScratchOffset()
4920 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDS1Addr1Offset()
4921 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } in selectDS1Addr1Offset()
4942 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, in selectDSReadWrite2()
4943 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, in selectDSReadWrite2()
4944 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); } in selectDSReadWrite2()
4999 static void addZeroImm(MachineInstrBuilder &MIB) { in addZeroImm() argument
5000 MIB.addImm(0); in addZeroImm()
5213 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFAddr64()
5214 MIB.addReg(RSrcReg); in selectMUBUFAddr64()
5216 [=](MachineInstrBuilder &MIB) { // vaddr in selectMUBUFAddr64()
5217 MIB.addReg(VAddr); in selectMUBUFAddr64()
5219 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFAddr64()
5221 MIB.addReg(SOffset); in selectMUBUFAddr64()
5223 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFAddr64()
5225 MIB.addImm(0); in selectMUBUFAddr64()
5227 [=](MachineInstrBuilder &MIB) { // offset in selectMUBUFAddr64()
5228 MIB.addImm(Offset); in selectMUBUFAddr64()
5246 [=](MachineInstrBuilder &MIB) { // rsrc in selectMUBUFOffset()
5247 MIB.addReg(RSrcReg); in selectMUBUFOffset()
5249 [=](MachineInstrBuilder &MIB) { // soffset in selectMUBUFOffset()
5251 MIB.addReg(SOffset); in selectMUBUFOffset()
5253 MIB.addReg(AMDGPU::SGPR_NULL); in selectMUBUFOffset()
5255 MIB.addImm(0); in selectMUBUFOffset()
5257 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset in selectMUBUFOffset()
5272 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}}; in selectBUFSOffset()
5296 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm()
5312 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }}; in selectSMRDBufferImm32()
5332 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }, in selectSMRDBufferSgprImm()
5333 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}}; in selectSMRDBufferSgprImm()
5465 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixModsExt()
5466 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMadMixModsExt()
5478 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3PMadMixMods()
5479 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods in selectVOP3PMadMixMods()
5586 MachineInstrBuilder MIB; in selectNamedBarrierInst() local
5588 MIB = BuildMI(*MBB, &I, DL, TII.get(Opc)); in selectNamedBarrierInst()
5591 MIB.addDef(I.getOperand(0).getReg()); in selectNamedBarrierInst()
5594 MIB.addImm(*BarValImm); in selectNamedBarrierInst()
5613 void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB, in renderTruncImm32() argument
5618 MIB.addImm(MI.getOperand(1).getCImm()->getSExtValue()); in renderTruncImm32()
5621 void AMDGPUInstructionSelector::renderNegateImm(MachineInstrBuilder &MIB, in renderNegateImm() argument
5626 MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue()); in renderNegateImm()
5629 void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB, in renderBitcastImm() argument
5636 MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); in renderBitcastImm()
5639 MIB.addImm(Op.getCImm()->getSExtValue()); in renderBitcastImm()
5643 void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB, in renderPopcntImm() argument
5648 MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount()); in renderPopcntImm()
5653 void AMDGPUInstructionSelector::renderTruncTImm(MachineInstrBuilder &MIB, in renderTruncTImm() argument
5656 MIB.addImm(MI.getOperand(OpIdx).getImm()); in renderTruncTImm()
5659 void AMDGPUInstructionSelector::renderOpSelTImm(MachineInstrBuilder &MIB, in renderOpSelTImm() argument
5663 MIB.addImm(MI.getOperand(OpIdx).getImm() ? (int64_t)SISrcMods::OP_SEL_0 : 0); in renderOpSelTImm()
5666 void AMDGPUInstructionSelector::renderExtractCPol(MachineInstrBuilder &MIB, in renderExtractCPol() argument
5670 MIB.addImm(MI.getOperand(OpIdx).getImm() & in renderExtractCPol()
5675 void AMDGPUInstructionSelector::renderExtractSWZ(MachineInstrBuilder &MIB, in renderExtractSWZ() argument
5682 MIB.addImm(Swizzle); in renderExtractSWZ()
5686 MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const { in renderExtractCpolSetGLC() argument
5691 MIB.addImm(Cpol | AMDGPU::CPol::GLC); in renderExtractCpolSetGLC()
5694 void AMDGPUInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB, in renderFrameIndex() argument
5697 MIB.addFrameIndex(MI.getOperand(1).getIndex()); in renderFrameIndex()
5700 void AMDGPUInstructionSelector::renderFPPow2ToExponent(MachineInstrBuilder &MIB, in renderFPPow2ToExponent() argument
5706 MIB.addImm(ExpVal); in renderFPPow2ToExponent()