Lines Matching refs:MIB
562 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
590 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
594 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
596 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
598 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
600 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
604 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
607 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
608 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
635 MIB.add(AM6Offset); in ExpandVLD()
648 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
649 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
656 MIB.add(MO); in ExpandVLD()
659 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
660 MIB.copyImplicitOps(MI); in ExpandVLD()
663 MIB.cloneMemRefs(MI); in ExpandVLD()
665 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); in ExpandVLD()
680 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST() local
684 MIB.add(MI.getOperand(OpIdx++)); in ExpandVST()
687 MIB.add(MI.getOperand(OpIdx++)); in ExpandVST()
688 MIB.add(MI.getOperand(OpIdx++)); in ExpandVST()
711 MIB.add(AM6Offset); in ExpandVST()
720 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
722 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
724 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
726 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
729 MIB.add(MI.getOperand(OpIdx++)); in ExpandVST()
730 MIB.add(MI.getOperand(OpIdx++)); in ExpandVST()
733 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandVST()
735 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
736 MIB.copyImplicitOps(MI); in ExpandVST()
739 MIB.cloneMemRefs(MI); in ExpandVST()
741 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); in ExpandVST()
757 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp() local
779 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
781 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
783 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
785 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
789 MIB.add(MI.getOperand(OpIdx++)); in ExpandLaneOp()
792 MIB.add(MI.getOperand(OpIdx++)); in ExpandLaneOp()
793 MIB.add(MI.getOperand(OpIdx++)); in ExpandLaneOp()
796 MIB.add(MI.getOperand(OpIdx++)); in ExpandLaneOp()
806 MIB.addReg(D0, SrcFlags); in ExpandLaneOp()
808 MIB.addReg(D1, SrcFlags); in ExpandLaneOp()
810 MIB.addReg(D2, SrcFlags); in ExpandLaneOp()
812 MIB.addReg(D3, SrcFlags); in ExpandLaneOp()
815 MIB.addImm(Lane); in ExpandLaneOp()
819 MIB.add(MI.getOperand(OpIdx++)); in ExpandLaneOp()
820 MIB.add(MI.getOperand(OpIdx++)); in ExpandLaneOp()
824 MIB.add(MO); in ExpandLaneOp()
827 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
828 MIB.copyImplicitOps(MI); in ExpandLaneOp()
830 MIB.cloneMemRefs(MI); in ExpandLaneOp()
842 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL() local
846 MIB.add(MI.getOperand(OpIdx++)); in ExpandVTBL()
849 MIB.add(VdSrc); in ExpandVTBL()
856 MIB.addReg(D0); in ExpandVTBL()
860 MIB.add(VmSrc); in ExpandVTBL()
863 MIB.add(MI.getOperand(OpIdx++)); in ExpandVTBL()
864 MIB.add(MI.getOperand(OpIdx++)); in ExpandVTBL()
867 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); in ExpandVTBL()
868 MIB.copyImplicitOps(MI); in ExpandVTBL()
870 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump();); in ExpandVTBL()
880 MachineInstrBuilder MIB = in ExpandMQQPRLoadStore() local
888 MIB.add(MI.getOperand(1)); in ExpandMQQPRLoadStore()
889 MIB.add(predOps(ARMCC::AL)); in ExpandMQQPRLoadStore()
890 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags); in ExpandMQQPRLoadStore()
891 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags); in ExpandMQQPRLoadStore()
892 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags); in ExpandMQQPRLoadStore()
893 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags); in ExpandMQQPRLoadStore()
896 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags); in ExpandMQQPRLoadStore()
897 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags); in ExpandMQQPRLoadStore()
898 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags); in ExpandMQQPRLoadStore()
899 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags); in ExpandMQQPRLoadStore()
903 MIB.addReg(SrcReg, RegState::Implicit); in ExpandMQQPRLoadStore()
905 MIB.copyImplicitOps(MI); in ExpandMQQPRLoadStore()
906 MIB.cloneMemRefs(MI); in ExpandMQQPRLoadStore()
1035 MachineInstrBuilder MIB = in ExpandTMOV32BitImm() local
1039 MIB.addReg(DstReg); in ExpandTMOV32BitImm()
1040 MIB.add(Operand); in ExpandTMOV32BitImm()
1041 MIB.add(predOps(ARMCC::AL)); in ExpandTMOV32BitImm()
1042 MIB.setMIFlags(MIFlags); in ExpandTMOV32BitImm()
1044 MIB.getInstr()->dump();); in ExpandTMOV32BitImm()
1842 MachineInstrBuilder MIB = in ExpandCMP_SWAP() local
1846 MIB.addImm(0); in ExpandCMP_SWAP()
1847 MIB.add(predOps(ARMCC::AL)); in ExpandCMP_SWAP()
1855 MachineInstrBuilder MIB; in ExpandCMP_SWAP() local
1856 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); in ExpandCMP_SWAP()
1857 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1859 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. in ExpandCMP_SWAP()
1860 MIB.add(predOps(ARMCC::AL)); in ExpandCMP_SWAP()
1879 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) in ExpandCMP_SWAP()
1883 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. in ExpandCMP_SWAP()
1884 MIB.add(predOps(ARMCC::AL)); in ExpandCMP_SWAP()
1924 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, in addExclusiveRegPair() argument
1930 MIB.addReg(RegLo, Flags); in addExclusiveRegPair()
1931 MIB.addReg(RegHi, Flags); in addExclusiveRegPair()
1933 MIB.addReg(Reg.getReg(), Flags); in addExclusiveRegPair()
1974 MachineInstrBuilder MIB; in ExpandCMP_SWAP_64() local
1975 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); in ExpandCMP_SWAP_64()
1976 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); in ExpandCMP_SWAP_64()
1977 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
2003 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); in ExpandCMP_SWAP_64()
2005 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI); in ExpandCMP_SWAP_64()
2006 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
2232 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); in ExpandMI() local
2234 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in ExpandMI()
2238 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in ExpandMI()
2244 MIB.add(predOps(ARMCC::AL)); in ExpandMI()
2578 MachineInstrBuilder MIB; in ExpandMI() local
2587 MIB = in ExpandMI()
2592 MIB.addImm(0); in ExpandMI()
2593 MIB.add(predOps(ARMCC::AL)); in ExpandMI()
2595 MIB = in ExpandMI()
2599 MIB.add(predOps(ARMCC::AL)); in ExpandMI()
2600 MIB.addReg(Reg, RegState::Kill); in ExpandMI()
2602 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandMI()
2605 MIB.add(predOps(ARMCC::AL)); in ExpandMI()
2606 MIB.addExternalSymbol("__aeabi_read_tp", 0); in ExpandMI()
2609 MIB.cloneMemRefs(MI); in ExpandMI()
2610 MIB.copyImplicitOps(MI); in ExpandMI()
2613 MF->moveCallSiteInfo(&MI, &*MIB); in ExpandMI()
2678 MachineInstrBuilder MIB = in ExpandMI() local
2682 MIB.addImm(0); in ExpandMI()
2683 MIB.add(predOps(ARMCC::AL)); in ExpandMI()
2686 MachineInstrBuilder MIB = in ExpandMI() local
2693 MIB.add(predOps(ARMCC::AL)); in ExpandMI()
2777 MachineInstrBuilder MIB = in ExpandMI() local
2786 MIB.add(MI.getOperand(OpIdx++)); in ExpandMI()
2789 MIB.add(MI.getOperand(OpIdx++)); in ExpandMI()
2790 MIB.add(MI.getOperand(OpIdx++)); in ExpandMI()
2795 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2799 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
2800 MIB.copyImplicitOps(MI); in ExpandMI()
2801 MIB.cloneMemRefs(MI); in ExpandMI()
2808 MachineInstrBuilder MIB = in ExpandMI() local
2818 MIB.add(Dst); in ExpandMI()
2821 MIB.add(MI.getOperand(OpIdx++)); in ExpandMI()
2822 MIB.add(MI.getOperand(OpIdx++)); in ExpandMI()
2827 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) in ExpandMI()
2831 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandMI()
2833 MIB.copyImplicitOps(MI); in ExpandMI()
2834 MIB.cloneMemRefs(MI); in ExpandMI()
3180 MachineInstrBuilder MIB; in ExpandMI() local
3188 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); in ExpandMI()
3198 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); in ExpandMI()
3200 MIB.cloneMemRefs(MI); in ExpandMI()
3202 MIB.add(MO); in ExpandMI()
3208 MachineInstrBuilder MIB = in ExpandMI() local
3210 MIB.cloneMemRefs(MI); in ExpandMI()
3212 MIB.add(MI.getOperand(i)); in ExpandMI()
3214 MF.moveCallSiteInfo(&MI, MIB.getInstr()); in ExpandMI()
3216 Bundler.append(MIB); in ExpandMI()
3226 MachineInstrBuilder MIB = in ExpandMI() local
3234 MIB.add(MO); in ExpandMI()
3235 MIB.add(predOps(ARMCC::AL)); in ExpandMI()
3236 MIB.cloneMemRefs(MI); in ExpandMI()