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Searched refs:LMUL (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp112 StringRef LMUL; in createInstruments() local
115 LMUL = "M1"; in createInstruments()
118 LMUL = "M2"; in createInstruments()
121 LMUL = "M4"; in createInstruments()
124 LMUL = "M8"; in createInstruments()
127 LMUL = "MF2"; in createInstruments()
130 LMUL = "MF4"; in createInstruments()
133 LMUL = "MF8"; in createInstruments()
140 createInstrument(RISCVLMULInstrument::DESC_NAME, LMUL)); in createInstruments()
169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL() argument
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h77 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { in isValidLMUL() argument
78 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1); in isValidLMUL()
92 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) { in encodeLMUL() argument
93 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL"); in encodeLMUL()
94 unsigned LmulLog2 = Log2_32(LMUL); in encodeLMUL()
/freebsd/contrib/llvm-project/clang/lib/Support/
H A DRISCVVIntrinsicUtils.cpp76 : BT(BT), LMUL(LMULType(Log2LMUL)) { in RVVType()
120 if (IsTuple && (1 << std::max(0, LMUL.Log2LMUL)) * NF > 8) in verifyType()
255 ClangBuiltinStr += utostr(ElementBitwidth) + LMUL.str() + in initClangBuiltinStr()
268 return Twine("v" + TypeStr + Twine(ElementBitwidth) + LMUL.str() + in initTypeStr()
356 ShortStr += LMUL.str(); in initShortStr()
679 Scale = LMUL.getScale(ElementBitwidth); in applyModifier()
708 LMUL.MulLog2LMUL(1); in applyModifier()
709 Scale = LMUL.getScale(ElementBitwidth); in applyModifier()
713 LMUL.MulLog2LMUL(2); in applyModifier()
714 Scale = LMUL.getScale(ElementBitwidth); in applyModifier()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h213 uint16_t LMUL : 3; member
222 uint16_t LMUL : 3; member
232 uint16_t LMUL : 3; member
241 uint16_t LMUL : 3; member
251 uint16_t LMUL : 3; member
259 uint16_t LMUL : 3; member
267 uint16_t LMUL : 3; member
H A DRISCVInsertVSETVLI.cpp221 } LMUL = LMULNone; member
228 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy; in usedVTYPE()
239 LMUL = LMULEqual; in demandVTYPE()
263 LMUL = std::max(LMUL, B.LMUL); in doUnion()
298 switch (LMUL) { in print()
326 static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) { in isLMUL1OrSmaller() argument
327 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL); in isLMUL1OrSmaller()
354 switch (Used.LMUL) { in areCompatibleVTYPEs()
423 Res.LMUL = DemandedFields::LMULNone; in getDemanded()
438 Res.LMUL = DemandedFields::LMULNone; in getDemanded()
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H A DRISCVVectorPeephole.cpp107 auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags)); in convertToVLMAX() local
109 unsigned LMULFixed = LMUL.second ? (8 / LMUL.first) : 8 * LMUL.first; in convertToVLMAX()
H A DRISCVScheduleV.td24 assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
39 // Helper function to get the largest LMUL from MxList
40 // Precondition: MxList is sorted in ascending LMUL order.
45 // Helper function to get the smallest SEW that can be used with LMUL mx
46 // Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>
117 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
151 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
192 // Define classes to define list containing all SchedWrites for each (name, LMUL)
193 // pair for each LMUL in each of the SchedMxList variants above and name in
195 // definitions of writes corresponding to each (name, LMUL) pair, that are needed
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H A DRISCVRegisterInfo.td365 // There is no need to define register classes for fractional LMUL.
371 // The set of legal NF for LMUL = lmul.
372 // LMUL <= 1, NF = 2, 3, 4, 5, 6, 7, 8
373 // LMUL == 2, NF = 2, 3, 4
374 // LMUL == 4, NF = 2
375 // LMUL == 8, no legal NF
394 // Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX.
396 // For example, when LMUL = 4, the potential valid indexes is
398 // NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0.
402 // Use START = 0, LMUL = 4 and NF = 2 as the example,
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H A DRISCVRegisterInfo.cpp316 unsigned LMUL = ZvlssegInfo->second; in lowerVSPILL() local
317 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations."); in lowerVSPILL()
319 switch (LMUL) { in lowerVSPILL()
346 int64_t Offset = VLENB * LMUL; in lowerVSPILL()
350 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVSPILL()
393 unsigned LMUL = ZvlssegInfo->second; in lowerVRELOAD() local
394 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations."); in lowerVRELOAD()
396 switch (LMUL) { in lowerVRELOAD()
423 int64_t Offset = VLENB * LMUL; in lowerVRELOAD()
427 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVRELOAD()
H A DRISCVSchedSiFive7.td12 /// On the SiFive7, the worst case LMUL is the Largest LMUL
13 /// and the worst case sew is the smallest SEW for that LMUL.
20 /// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
21 /// and the worst case sew is the smallest SEW for that LMUL.
29 /// Number of DLEN parts = (LMUL * VLEN) / DLEN.
30 /// Since DLEN = VLEN / 2, Num DLEN parts = 2 * LMUL.
67 /// 2 DLENs when LMUL=8. 1 DLEN for all other DLENs
76 // formula (2 * VLEN * LMUL) / DLEN = 4 * LMUL
94 // (VLEN * LMUL) / SEW
114 // c = ceil(VLEN / SEW) * LMUL
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H A DRISCVISelDAGToDAG.cpp240 unsigned NF, RISCVII::VLMUL LMUL) { in createTuple() argument
253 switch (LMUL) { in createTuple()
345 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG() local
352 SDValue Merge = createTuple(*CurDAG, Regs, NF, LMUL); in selectVLSEG()
361 static_cast<unsigned>(LMUL)); in selectVLSEG()
385 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF() local
392 SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); in selectVLSEGFF()
402 Log2SEW, static_cast<unsigned>(LMUL)); in selectVLSEGFF()
427 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG() local
434 SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); in selectVLXSEG()
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H A DRISCVInstrInfo.cpp252 // LMUL = 1/2/4/8. We should be able to convert vmv1r.v to vmv.v.v in isConvertibleToVMV_V_V()
253 // for fractional LMUL operations. However, we could not use the vsetvli in isConvertibleToVMV_V_V()
255 // 2 x LMUL. in isConvertibleToVMV_V_V()
271 // We only permit the source of COPY has the same LMUL as the defined in isConvertibleToVMV_V_V()
273 // There are cases we need to keep the whole register copy if the LMUL in isConvertibleToVMV_V_V()
289 // only checking the LMUL is insufficient due to reduction result is in isConvertibleToVMV_V_V()
349 // DstEncoding and SrcEncoding should be >= LMUL value we try to use to in copyPhysRegVector()
395 // aligned to larger LMUL, we can eliminate some copyings. in copyPhysRegVector()
3024 #define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL) \
3025 RISCV::Pseudo##OP##_##LMUL
3017 CASE_RVV_OPCODE_UNMASK_LMUL(OP,LMUL) global() argument
3020 CASE_RVV_OPCODE_MASK_LMUL(OP,LMUL) global() argument
3023 CASE_RVV_OPCODE_LMUL(OP,LMUL) global() argument
3061 CASE_VMA_OPCODE_COMMON(OP,TYPE,LMUL) global() argument
3083 CASE_VFMA_OPCODE_COMMON(OP,TYPE,LMUL,SEW) global() argument
3274 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP,NEWOP,TYPE,LMUL) global() argument
3303 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP,NEWOP,TYPE,LMUL,SEW) global() argument
3474 CASE_WIDEOP_OPCODE_COMMON(OP,LMUL) global() argument
3488 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP,LMUL) global() argument
3505 CASE_FP_WIDEOP_OPCODE_COMMON(OP,LMUL,SEW) global() argument
3519 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP,LMUL,SEW) global() argument
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H A DRISCVInstrInfoVPseudos.td20 /// LMUL/EMUL - Most instructions can write to differently sized register groups
21 /// depending on LMUL.
139 // This class describes information associated to the LMUL.
152 // Associate LMUL with tablegen records of register classes.
388 // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will
401 // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
584 bits<3> LMUL = L;
596 let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
597 let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"];
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H A DRISCVSchedSiFiveP600.td12 /// On the SiFiveP600, the worst case LMUL is the Largest LMUL
13 /// and the worst case sew is the smallest SEW for that LMUL.
956 // LMUL Aware
1081 // LMUL Aware
H A DRISCVTargetTransformInfo.cpp318 unsigned LMUL = in getRegisterBitWidth() local
325 ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0); in getRegisterBitWidth()
330 ? LMUL * RISCV::RVVBitsPerBlock in getRegisterBitWidth()
H A DRISCVInstrInfoV.td120 // The scheudling resources are relevant to LMUL and may be relevant to SEW.
1174 // group cannot overlap the mask register if used, unless LMUL=1.
H A DRISCVISelLowering.cpp166 // Disable the smallest fractional LMUL types if ELEN is less than in RISCVTargetLowering()
1554 // The maximum VF is for the smallest element width with LMUL=8. in shouldExpandGetVectorLength()
2457 llvm_unreachable("Invalid LMUL."); in getLMUL()
2478 llvm_unreachable("Invalid LMUL."); in getRegClassIDForLMUL()
2494 RISCVII::VLMUL LMUL = getLMUL(VT); in getSubregIndexByMVT()
2495 if (LMUL == RISCVII::VLMUL::LMUL_F8 || in getSubregIndexByMVT()
2496 LMUL == RISCVII::VLMUL::LMUL_F4 || in getSubregIndexByMVT()
2497 LMUL == RISCVII::VLMUL::LMUL_F2 || in getSubregIndexByMVT()
2498 LMUL == RISCVII::VLMUL::LMUL_1) { in getSubregIndexByMVT()
2503 if (LMUL in getSubregIndexByMVT()
2493 RISCVII::VLMUL LMUL = getLMUL(VT); getSubregIndexByMVT() local
8859 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT); lowerVectorIntrinsicScalars() local
8874 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT); lowerVectorIntrinsicScalars() local
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H A DRISCVInstrInfoXTHead.td468 // Associate LMUL with tablegen records of register classes.
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h58 // Corresponds to LMUL instruction
59 LMUL, enumerator
H A DXCoreISelLowering.cpp59 case XCoreISD::LMUL : return "XCoreISD::LMUL"; in getTargetNodeName()
556 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, in LowerUMUL_LOHI()
1609 case XCoreISD::LMUL: { in PerformDAGCombine()
1621 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), in PerformDAGCombine()
1649 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, in PerformDAGCombine()
1674 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, in PerformDAGCombine()
H A DXCoreISelDAGToDAG.cpp205 case XCoreISD::LMUL: { in Select()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td612 // and LMUL.
2328 // Reinterpret between different type under the same SEW and LMUL
2348 // Reinterpret between different SEW under the same LMUL
2358 // and same LMUL has the implicit assumption that if FixedSEW is set to the
2363 // Reinterpret from LMUL=1 integer type to vector boolean type
2373 // Reinterpret from vector boolean type to LMUL=1 integer type
2384 // Reinterpret from LMUL=1 integer type to vector boolean type
2393 // Reinterpret from vector boolean type to LMUL=1 integer type
2427 // LMUL truncation
2447 // LMUL extension
H A DAttrDocs.td2463 ``N==(__riscv_v_fixed_vlen*LMUL)``, the implementation defined feature macro that
2467 For types where LMUL!=1, ``__riscv_v_fixed_vlen`` needs to be scaled by the LMUL
/freebsd/contrib/llvm-project/clang/include/clang/Support/
H A DRISCVVIntrinsicUtils.h256 LMULType LMUL; variable
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGDebugInfo.cpp814 unsigned LMUL; in CreateType() local
818 LMUL = 1; in CreateType()
822 LMUL = 64 / FixedSize; in CreateType()
824 LMUL = FixedSize / 64; in CreateType()
837 llvm::dwarf::DW_OP_div, llvm::dwarf::DW_OP_constu, LMUL}); in CreateType()

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