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Searched refs:LMUL (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp126 StringRef LMUL; in createInstruments() local
129 LMUL = "M1"; in createInstruments()
132 LMUL = "M2"; in createInstruments()
135 LMUL = "M4"; in createInstruments()
138 LMUL = "M8"; in createInstruments()
141 LMUL = "MF2"; in createInstruments()
144 LMUL = "MF4"; in createInstruments()
147 LMUL = "MF8"; in createInstruments()
154 createInstrument(RISCVLMULInstrument::DESC_NAME, LMUL)); in createInstruments()
183 getEEWAndEMUL(unsigned Opcode, RISCVVType::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL() argument
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h96 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { in isValidLMUL() argument
97 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1); in isValidLMUL()
113 inline static VLMUL encodeLMUL(unsigned LMUL, bool Fractional) { in encodeLMUL() argument
114 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL"); in encodeLMUL()
115 unsigned LmulLog2 = Log2_32(LMUL); in encodeLMUL()
/freebsd/contrib/llvm-project/clang/lib/Support/
H A DRISCVVIntrinsicUtils.cpp73 : BT(BT), LMUL(LMULType(Log2LMUL)) { in RVVType()
117 if (IsTuple && (1 << std::max(0, LMUL.Log2LMUL)) * NF > 8) in verifyType()
252 ClangBuiltinStr += utostr(ElementBitwidth) + LMUL.str() + in initClangBuiltinStr()
265 return Twine("v" + TypeStr + Twine(ElementBitwidth) + LMUL.str() + in initTypeStr()
353 ShortStr += LMUL.str(); in initShortStr()
676 Scale = LMUL.getScale(ElementBitwidth); in applyModifier()
705 LMUL.MulLog2LMUL(1); in applyModifier()
706 Scale = LMUL.getScale(ElementBitwidth); in applyModifier()
710 LMUL.MulLog2LMUL(2); in applyModifier()
711 Scale = LMUL.getScale(ElementBitwidth); in applyModifier()
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector_common.td21 // range of which is specified by the cross product of the LMUL attribute and
22 // every element in the attribute TypeRange. By default builtins have LMUL = [1,
24 // use the Log2LMUL [0, 1, 2, 3, -1, -2, -3] to represent the LMUL.
26 // LMUL represents the fact that the types of values used by that builtin are
27 // values generated by instructions that are executed under that LMUL. However,
29 // that executes under the specified LMUL. An example where this happens are
31 // instance, by comparing two `__rvv_int8m1_t` (this is LMUL=1) or comparing two
32 // `__rvv_int16m2_t` (this is LMUL=2). The actual load or store, however, will
33 // be performed under LMUL=1 because mask registers are not grouped.
46 // This way, given an LMUL, a record with a TypeRange "sil" will cause the
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H A Driscv_vector.td418 // and LMUL.
1652 // Reinterpret between different type under the same SEW and LMUL
1664 // Reinterpret between different SEW under the same LMUL
1674 // and same LMUL has the implicit assumption that if FixedSEW is set to the
1679 // Reinterpret from LMUL=1 integer type to vector boolean type
1689 // Reinterpret from vector boolean type to LMUL=1 integer type
1700 // Reinterpret from LMUL=1 integer type to vector boolean type
1709 // Reinterpret from vector boolean type to LMUL=1 integer type
1739 // LMUL truncation
1756 // LMUL extension
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h692 uint16_t LMUL : 3; member
701 uint16_t LMUL : 3; member
711 uint16_t LMUL : 3; member
720 uint16_t LMUL : 3; member
730 uint16_t LMUL : 3; member
738 uint16_t LMUL : 3; member
746 uint16_t LMUL : 3; member
755 uint16_t LMUL : 3; member
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td589 // There is no need to define register classes for fractional LMUL.
595 // The set of legal NF for LMUL = lmul.
596 // LMUL <= 1, NF = 2, 3, 4, 5, 6, 7, 8
597 // LMUL == 2, NF = 2, 3, 4
598 // LMUL == 4, NF = 2
599 // LMUL == 8, no legal NF
618 // Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX.
620 // For example, when LMUL = 4, the potential valid indexes is
622 // NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0.
626 // Use START = 0, LMUL = 4 and NF = 2 as the example,
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H A DRISCVInsertVSETVLI.cpp160 } LMUL = LMULNone; member
170 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy || VILL; in usedVTYPE()
181 LMUL = LMULEqual; in demandVTYPE()
206 LMUL = std::max(LMUL, B.LMUL); in doUnion()
242 switch (LMUL) { in print()
271 static bool isLMUL1OrSmaller(RISCVVType::VLMUL LMUL) { in isLMUL1OrSmaller() argument
272 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL); in isLMUL1OrSmaller()
299 switch (Used.LMUL) { in areCompatibleVTYPEs()
368 Res.LMUL = DemandedFields::LMULNone; in getDemanded()
383 Res.LMUL = DemandedFields::LMULNone; in getDemanded()
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H A DRISCVScheduleV.td24 assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
39 // Helper function to get the largest LMUL from MxList
40 // Precondition: MxList is sorted in ascending LMUL order.
45 // Helper function to get the smallest SEW that can be used with LMUL mx
46 // Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>
117 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
151 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
192 // Define classes to define list containing all SchedWrites for each (name, LMUL)
193 // pair for each LMUL in each of the SchedMxList variants above and name in
195 // definitions of writes corresponding to each (name, LMUL) pair, that are needed
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H A DRISCVRegisterInfo.cpp405 unsigned LMUL = ZvlssegInfo->second; in lowerVSPILL() local
406 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations."); in lowerVSPILL()
408 switch (LMUL) { in lowerVSPILL()
435 int64_t Offset = VLENB * LMUL; in lowerVSPILL()
439 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVSPILL()
488 unsigned LMUL = ZvlssegInfo->second; in lowerVRELOAD() local
489 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations."); in lowerVRELOAD()
491 switch (LMUL) { in lowerVRELOAD()
518 int64_t Offset = VLENB * LMUL; in lowerVRELOAD()
522 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVRELOAD()
H A DRISCVSchedSiFive7.td12 /// On the SiFive7, the worst case LMUL is the Largest LMUL
13 /// and the worst case sew is the smallest SEW for that LMUL.
20 /// MxList. On the SiFive7, the worst case LMUL is the Largest LMUL
21 /// and the worst case sew is the smallest SEW for that LMUL.
29 /// Number of DLEN parts = (LMUL * VLEN) / DLEN.
30 /// Since DLEN = VLEN / 2, Num DLEN parts = 2 * LMUL.
67 /// 2 DLENs when LMUL=8. 1 DLEN for all other DLENs
76 // formula (2 * VLEN * LMUL) / DLEN = 4 * LMUL
93 // (VLEN * LMUL) / SEW
110 // c = ceil(VLEN / SEW) * LMUL
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H A DRISCVInstrInfo.cpp170 unsigned LMUL = *getLMULForRVVWholeLoadStore(MI.getOpcode()); in isLoadFromStackSlot() local
171 MemBytes = TypeSize::getScalable(RISCV::RVVBytesPerBlock * LMUL); in isLoadFromStackSlot()
221 unsigned LMUL = *getLMULForRVVWholeLoadStore(MI.getOpcode()); in isStoreToStackSlot() local
222 MemBytes = TypeSize::getScalable(RISCV::RVVBytesPerBlock * LMUL); in isStoreToStackSlot()
3646 #define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL) \ argument
3647 RISCV::Pseudo##OP##_##LMUL
3649 #define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL) \ argument
3650 RISCV::Pseudo##OP##_##LMUL##_MASK
3652 #define CASE_RVV_OPCODE_LMUL(OP, LMUL) \ argument
3653 CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL): \
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H A DRISCVISelDAGToDAG.cpp287 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG() local
299 static_cast<unsigned>(LMUL)); in selectVLSEG()
316 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF() local
329 Log2SEW, static_cast<unsigned>(LMUL)); in selectVLSEGFF()
346 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG() local
361 auto DecodedLMUL = RISCVVType::decodeVLMUL(LMUL); in selectVLXSEG()
377 NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL), in selectVLXSEG()
394 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSSEG() local
405 NF, IsMasked, IsStrided, Log2SEW, static_cast<unsigned>(LMUL)); in selectVSSEG()
419 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSXSEG() local
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H A DRISCVSchedSiFiveP400.td12 /// On the SiFiveP400, the worst case LMUL is the Largest LMUL
13 /// and the worst case sew is the smallest SEW for that LMUL.
41 defvar LMUL = SiFiveP400GetLMulCycles<mx>.c;
46 true: !div(!mul(SiFiveP400VLEN, LMUL), sew)
70 // The latency for simple unordered VFReduce is `C + 6 * log2(LMUL)`,
71 // and `C * LMUL` for ordered VFReduce. This helper class provides the `C`.
93 // TODO: Fractional LMUL's latency and rthroughput.
127 // c = ceil(LMUL / 2)
648 // Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.
885 // The worst case for Zvknh[ab] is designated to the largest SEW and LMUL.
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H A DRISCVVectorPeephole.cpp218 auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags)); in convertToVLMAX() local
220 unsigned LMULFixed = LMUL.second ? (8 / LMUL.first) : 8 * LMUL.first; in convertToVLMAX()
H A DRISCVSchedSiFiveP800.td12 /// On the SiFiveP800, the worst case LMUL is the Largest LMUL
13 /// and the worst case sew is the smallest SEW for that LMUL.
53 // c = ceil(LMUL / 2)
610 // Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.
722 // to be different in non-trivial LMUL. Update to the correct numbers here.
828 // The worst case for Zvknh[ab] is designated to the largest SEW and LMUL.
1001 // LMUL Aware
1126 // LMUL Aware
H A DRISCVInstrInfoVPseudos.td20 /// LMUL/EMUL - Most instructions can write to differently sized register groups
21 /// depending on LMUL.
168 // This class describes information associated to the LMUL.
181 // Associate LMUL with tablegen records of register classes.
411 // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will
424 // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
606 bits<3> LMUL = L;
618 let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
619 let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"];
627 bits<3> LMUL = L;
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H A DRISCVSchedSiFiveP600.td12 /// On the SiFiveP600, the worst case LMUL is the Largest LMUL
13 /// and the worst case sew is the smallest SEW for that LMUL.
41 defvar LMUL = SiFiveP600GetLMulCycles<mx>.c;
46 true: !div(!mul(SiFiveP600VLEN, LMUL), sew)
68 // c = ceil(LMUL / 2)
872 // Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.
1137 // The worst case for Zvknh[ab] is designated to the largest SEW and LMUL.
1312 // LMUL Aware
1437 // LMUL Aware
H A DRISCVInterleavedAccess.cpp53 auto [LMUL, Fractional] = RISCVVType::decodeVLMUL(getLMUL(ContainerVT)); in isLegalInterleavedAccessType()
56 return Factor * LMUL <= 8; in isLegalInterleavedAccessType()
H A DRISCVTargetTransformInfo.cpp348 unsigned LMUL = in getRegisterBitWidth() local
355 ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0); in getRegisterBitWidth()
360 ? LMUL * RISCV::RVVBitsPerBlock in getRegisterBitWidth()
920 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in isM1OrSmaller() local
921 return (LMUL == RISCVVType::VLMUL::LMUL_F8 || in isM1OrSmaller()
922 LMUL == RISCVVType::VLMUL::LMUL_F4 || in isM1OrSmaller()
923 LMUL == RISCVVType::VLMUL::LMUL_F2 || in isM1OrSmaller()
924 LMUL == RISCVVType::VLMUL::LMUL_1); in isM1OrSmaller()
H A DRISCVInstrInfoXAndes.td75 bits<3> LMUL = L;
82 let Fields = ["Masked", "Unsigned", "Log2SEW", "LMUL", "Pseudo"];
83 let PrimaryKey = ["Masked", "Unsigned", "Log2SEW", "LMUL"];
/freebsd/crypto/openssl/crypto/modes/asm/
H A Daes-gcm-riscv64-zvkb-zvkg-zvkned.pl403 # FULL_BLOCK_LEN32 = (VLEN*LMUL)/(EGW) * (EGW/SEW) = (VLEN*4)/(32*4) * 4
413 ## n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4))
/freebsd/crypto/openssl/crypto/aes/asm/
H A Daes-riscv64-zvbb-zvkg-zvkned.pl154 # n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4))
/freebsd/contrib/llvm-project/clang/include/clang/Support/
H A DRISCVVIntrinsicUtils.h256 LMULType LMUL; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp529 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, in LowerUMUL_LOHI()
1580 case XCoreISD::LMUL: { in PerformDAGCombine()
1592 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), in PerformDAGCombine()
1620 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, in PerformDAGCombine()
1645 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, in PerformDAGCombine()

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