Lines Matching refs:LMUL
20 /// LMUL/EMUL - Most instructions can write to differently sized register groups
21 /// depending on LMUL.
139 // This class describes information associated to the LMUL.
152 // Associate LMUL with tablegen records of register classes.
388 // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will
401 // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
584 bits<3> LMUL = L;
596 let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
597 let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"];
605 bits<3> LMUL = L;
612 let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
613 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
621 bits<3> LMUL = L;
633 let Fields = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
634 let PrimaryKey = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
653 bits<3> LMUL = L;
660 let Fields = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
661 let PrimaryKey = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL"];
670 bits<3> LMUL = L;
678 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
679 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
688 bits<3> LMUL = L;
695 let Fields = ["NF", "Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
696 let PrimaryKey = ["NF", "Masked", "Strided", "Log2SEW", "LMUL"];
705 bits<3> LMUL = L;
713 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
714 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
866 bits<3> LMUL,
874 RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
888 bits<3> LMUL,
897 RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1327 class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
1333 RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1341 class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
1347 RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1693 bits<3> LMUL,
1700 RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1715 bits<3> LMUL,
1723 RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1798 bits<3> LMUL,
1805 RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1816 bits<3> LMUL,
1823 RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
2360 // if the source and destination have an LMUL<=1. This matches this overlap
2624 // We don't need @earlyclobber for LMUL<=1 since that matches this overlap
2628 // With LMUL<=1 the source and dest occupy a single register so any overlap