Searched refs:ItinList (Results 1 – 14 of 14) sorted by relevance
14 list<InstrItinData> ItinList =24 [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>;
16 list<InstrItinData> ItinList =27 HexagonV69ItinList.ItinList>;
15 list<InstrItinData> ItinList =26 HexagonV71ItinList.ItinList>;
15 list<InstrItinData> ItinList =26 HexagonV73ItinList.ItinList>;
27 list<InstrItinData> ItinList =33 [Hex_FWD], HexagonV5ItinList.ItinList>;
28 list<InstrItinData> ItinList =35 [Hex_FWD], HexagonV55ItinList.ItinList>;
16 list<InstrItinData> ItinList =27 HexagonV65ItinList.ItinList>;
16 list<InstrItinData> ItinList =27 HexagonV66ItinList.ItinList>;
16 list<InstrItinData> ItinList =27 HexagonV67ItinList.ItinList>;
15 list<InstrItinData> ItinList =26 HexagonV68ItinList.ItinList>;
37 list<InstrItinData> ItinList =49 HexagonV67TItinList.ItinList>;
37 list<InstrItinData> ItinList =48 HexagonV71TItinList.ItinList>;
58 list<InstrItinData> ItinList =68 [Hex_FWD, HVX_FWD], HexagonV60ItinList.ItinList>;
500 std::vector<InstrItinerary> &ItinList = ProcItinLists.emplace_back(); in EmitStageAndOperandCycleData() local509 ItinList.resize(SchedModels.numInstrSchedClasses()); in EmitStageAndOperandCycleData()510 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()512 for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size(); in EmitStageAndOperandCycleData()587 ItinList[SchedClassIdx] = Intinerary; in EmitStageAndOperandCycleData()632 std::vector<InstrItinerary> &ItinList = *ProcItinListsIter; in EmitItineraries() local636 if (ItinList.empty()) in EmitItineraries()646 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { in EmitItineraries()647 InstrItinerary &Intinerary = ItinList[j]; in EmitItineraries()