1*0b57cec5SDimitry Andric//=-HexagonScheduleV5.td - HexagonV5 Scheduling Definitions --*- tablegen -*-=// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andricdef LD_tc_ld_SLOT01 : InstrItinClass; 10*0b57cec5SDimitry Andricdef ST_tc_st_SLOT01 : InstrItinClass; 11*0b57cec5SDimitry Andric 12*0b57cec5SDimitry Andricclass HexagonV5PseudoItin { 13*0b57cec5SDimitry Andric list<InstrItinData> V5PseudoItin_list = [ 14*0b57cec5SDimitry Andric InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 15*0b57cec5SDimitry Andric InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 16*0b57cec5SDimitry Andric InstrStage<1, [SLOT2, SLOT3]>]>, 17*0b57cec5SDimitry Andric InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>, 18*0b57cec5SDimitry Andric InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]> 19*0b57cec5SDimitry Andric ]; 20*0b57cec5SDimitry Andric} 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andricdef HexagonV5ItinList : DepScalarItinV5, HexagonV5PseudoItin { 23*0b57cec5SDimitry Andric list<InstrItinData> V5Itin_list = [ 24*0b57cec5SDimitry Andric InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>, 25*0b57cec5SDimitry Andric InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]> 26*0b57cec5SDimitry Andric ]; 27*0b57cec5SDimitry Andric list<InstrItinData> ItinList = 28*0b57cec5SDimitry Andric !listconcat(V5Itin_list, DepScalarItinV5_list, V5PseudoItin_list); 29*0b57cec5SDimitry Andric} 30*0b57cec5SDimitry Andric 31*0b57cec5SDimitry Andricdef HexagonItinerariesV5 : 32*0b57cec5SDimitry Andric ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], 33*0b57cec5SDimitry Andric [Hex_FWD], HexagonV5ItinList.ItinList>; 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andricdef HexagonModelV5 : SchedMachineModel { 36*0b57cec5SDimitry Andric // Max issue per cycle == bundle width. 37*0b57cec5SDimitry Andric let IssueWidth = 4; 38*0b57cec5SDimitry Andric let Itineraries = HexagonItinerariesV5; 39*0b57cec5SDimitry Andric let LoadLatency = 1; 40*0b57cec5SDimitry Andric let CompleteModel = 0; 41*0b57cec5SDimitry Andric} 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 44*0b57cec5SDimitry Andric// Hexagon V5 Resource Definitions - 45*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 46