1*0b57cec5SDimitry Andric//=-HexagonScheduleV55.td - HexagonV55 Scheduling Definitions -*- tablegen -*=// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric 10*0b57cec5SDimitry Andricclass HexagonV55PseudoItin { 11*0b57cec5SDimitry Andric list<InstrItinData> V55PseudoItin_list = [ 12*0b57cec5SDimitry Andric InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], 13*0b57cec5SDimitry Andric [1, 1, 1]>, 14*0b57cec5SDimitry Andric InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 15*0b57cec5SDimitry Andric InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>, 16*0b57cec5SDimitry Andric InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>, 17*0b57cec5SDimitry Andric InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]> 18*0b57cec5SDimitry Andric ]; 19*0b57cec5SDimitry Andric} 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andricdef HexagonV55ItinList : DepScalarItinV55, 22*0b57cec5SDimitry Andric HexagonV55PseudoItin { 23*0b57cec5SDimitry Andric list<InstrItinData> V55Itin_list = [ 24*0b57cec5SDimitry Andric InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>, 25*0b57cec5SDimitry Andric InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], 26*0b57cec5SDimitry Andric [1, 1, 1]> 27*0b57cec5SDimitry Andric ]; 28*0b57cec5SDimitry Andric list<InstrItinData> ItinList = 29*0b57cec5SDimitry Andric !listconcat(V55Itin_list, DepScalarItinV55_list, 30*0b57cec5SDimitry Andric V55PseudoItin_list); 31*0b57cec5SDimitry Andric} 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andricdef HexagonItinerariesV55 : 34*0b57cec5SDimitry Andric ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], 35*0b57cec5SDimitry Andric [Hex_FWD], HexagonV55ItinList.ItinList>; 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andricdef HexagonModelV55 : SchedMachineModel { 38*0b57cec5SDimitry Andric // Max issue per cycle == bundle width. 39*0b57cec5SDimitry Andric let IssueWidth = 4; 40*0b57cec5SDimitry Andric let Itineraries = HexagonItinerariesV55; 41*0b57cec5SDimitry Andric let LoadLatency = 1; 42*0b57cec5SDimitry Andric let CompleteModel = 0; 43*0b57cec5SDimitry Andric} 44*0b57cec5SDimitry Andric 45*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 46*0b57cec5SDimitry Andric// Hexagon V55 Resource Definitions - 47*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 48