xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV65.td (revision 0b57cec536236d46e3dba9bd041533462f33dbb7)
1*0b57cec5SDimitry Andric//=-HexagonScheduleV65.td - HexagonV65 Scheduling Definitions *- tablegen -*-=//
2*0b57cec5SDimitry Andric//
3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric//
7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric
9*0b57cec5SDimitry Andric//
10*0b57cec5SDimitry Andric// ScalarItin and HVXItin contain some old itineraries
11*0b57cec5SDimitry Andric// still used by a handful of instructions. Hopefully, we will be able
12*0b57cec5SDimitry Andric// to get rid of them soon.
13*0b57cec5SDimitry Andric
14*0b57cec5SDimitry Andricdef HexagonV65ItinList : DepScalarItinV65, ScalarItin,
15*0b57cec5SDimitry Andric                         DepHVXItinV65, HVXItin, PseudoItin {
16*0b57cec5SDimitry Andric  list<InstrItinData> ItinList =
17*0b57cec5SDimitry Andric    !listconcat(DepScalarItinV65_list, ScalarItin_list,
18*0b57cec5SDimitry Andric                DepHVXItinV65_list, HVXItin_list, PseudoItin_list);
19*0b57cec5SDimitry Andric}
20*0b57cec5SDimitry Andric
21*0b57cec5SDimitry Andricdef HexagonItinerariesV65 :
22*0b57cec5SDimitry Andric      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
23*0b57cec5SDimitry Andric                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
24*0b57cec5SDimitry Andric                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
25*0b57cec5SDimitry Andric                            CVI_ALL_NOMEM, CVI_ZW],
26*0b57cec5SDimitry Andric                            [Hex_FWD, HVX_FWD],
27*0b57cec5SDimitry Andric                            HexagonV65ItinList.ItinList>;
28*0b57cec5SDimitry Andric
29*0b57cec5SDimitry Andricdef HexagonModelV65 : SchedMachineModel {
30*0b57cec5SDimitry Andric  // Max issue per cycle == bundle width.
31*0b57cec5SDimitry Andric  let IssueWidth = 4;
32*0b57cec5SDimitry Andric  let Itineraries = HexagonItinerariesV65;
33*0b57cec5SDimitry Andric  let LoadLatency = 1;
34*0b57cec5SDimitry Andric  let CompleteModel = 0;
35*0b57cec5SDimitry Andric}
36*0b57cec5SDimitry Andric
37*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
38*0b57cec5SDimitry Andric// Hexagon V65 Resource Definitions -
39*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
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