xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV71.td (revision bdd1243df58e60e85101c09001d9812a789b6bc4)
1*bdd1243dSDimitry Andric//=-HexagonScheduleV71.td - HexagonV71 Scheduling Definitions *- tablegen -*-=//
2*bdd1243dSDimitry Andric//
3*bdd1243dSDimitry Andric//                     The LLVM Compiler Infrastructure
4*bdd1243dSDimitry Andric//
5*bdd1243dSDimitry Andric// This file is distributed under the University of Illinois Open Source
6*bdd1243dSDimitry Andric// License. See LICENSE.TXT for details.
7*bdd1243dSDimitry Andric//
8*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===//
9*bdd1243dSDimitry Andric
10*bdd1243dSDimitry Andric//
11*bdd1243dSDimitry Andric// ScalarItin and HVXItin contain some old itineraries still used by a handful
12*bdd1243dSDimitry Andric// of instructions. Hopefully, we will be able to get rid of them soon.
13*bdd1243dSDimitry Andricdef HexagonV71ItinList : DepScalarItinV71, ScalarItin,
14*bdd1243dSDimitry Andric                         DepHVXItinV71, HVXItin, PseudoItin {
15*bdd1243dSDimitry Andric  list<InstrItinData> ItinList =
16*bdd1243dSDimitry Andric    !listconcat(DepScalarItinV71_list, ScalarItin_list,
17*bdd1243dSDimitry Andric                DepHVXItinV71_list, HVXItin_list, PseudoItin_list);
18*bdd1243dSDimitry Andric}
19*bdd1243dSDimitry Andric
20*bdd1243dSDimitry Andricdef HexagonItinerariesV71 :
21*bdd1243dSDimitry Andric      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
22*bdd1243dSDimitry Andric                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
23*bdd1243dSDimitry Andric                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
24*bdd1243dSDimitry Andric                            CVI_ALL_NOMEM, CVI_ZW],
25*bdd1243dSDimitry Andric                            [Hex_FWD, HVX_FWD],
26*bdd1243dSDimitry Andric                            HexagonV71ItinList.ItinList>;
27*bdd1243dSDimitry Andric
28*bdd1243dSDimitry Andricdef HexagonModelV71 : SchedMachineModel {
29*bdd1243dSDimitry Andric  // Max issue per cycle == bundle width.
30*bdd1243dSDimitry Andric  let IssueWidth = 4;
31*bdd1243dSDimitry Andric  let Itineraries = HexagonItinerariesV71;
32*bdd1243dSDimitry Andric  let LoadLatency = 1;
33*bdd1243dSDimitry Andric  let CompleteModel = 0;
34*bdd1243dSDimitry Andric}
35*bdd1243dSDimitry Andric
36*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===//
37*bdd1243dSDimitry Andric// Hexagon V71 Resource Definitions -
38*bdd1243dSDimitry Andric//===----------------------------------------------------------------------===//
39*bdd1243dSDimitry Andric
40