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Searched refs:IssueWidth (Results 1 – 25 of 102) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp73 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
105 if (IssueWidth == 0) in atIssueLimit()
108 return IssueCount == IssueWidth; in atIssueLimit()
H A DTargetSchedule.cpp59 ResourceLCM = SchedModel.IssueWidth; in init()
65 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachinePipeliner.h475 int IssueWidth; variable
505 IssueWidth(SM.IssueWidth) { in ResourceManager()
507 if (IssueWidth <= 0) in ResourceManager()
509 IssueWidth = 100; in ResourceManager()
511 IssueWidth = SwpForceIssueWidth; in ResourceManager()
H A DScoreboardHazardRecognizer.h100 unsigned IssueWidth = 0; variable
H A DTargetSchedule.h70 /// This is more detailed than the course grain IssueWidth and default
98 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp108 return ((double)SCDesc.NumMicroOps) / SM.IssueWidth; in getReciprocalThroughput()
121 return 1.0 / IssueWidth; in getReciprocalThroughput()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp221 unsigned IssueWidth = TSM.getIssueWidth(); in addPadding() local
223 for (unsigned i = 0, e = IssueWidth * NOOPsToAdd; i != e; ++i) in addPadding()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV62.td28 let IssueWidth = 4;
H A DHexagonScheduleV69.td31 let IssueWidth = 4;
H A DHexagonScheduleV71.td30 let IssueWidth = 4;
H A DHexagonScheduleV73.td30 let IssueWidth = 4;
H A DHexagonScheduleV5.td37 let IssueWidth = 4;
H A DHexagonScheduleV55.td39 let IssueWidth = 4;
H A DHexagonScheduleV65.td31 let IssueWidth = 4;
H A DHexagonScheduleV66.td31 let IssueWidth = 4;
H A DHexagonScheduleV67.td31 let IssueWidth = 4;
H A DHexagonScheduleV68.td30 let IssueWidth = 4;
H A DHexagonScheduleV67T.td53 let IssueWidth = 3;
H A DHexagonScheduleV71T.td51 let IssueWidth = 3;
H A DHexagonScheduleV60.td72 let IssueWidth = 4;
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DSummaryView.cpp27 : SM(Model), Source(S), DispatchWidth(Width ? Width : Model.IssueWidth), in SummaryView()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td39 let IssueWidth = 1;
/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h254 // IssueWidth is the maximum number of instructions that may be scheduled in
257 // IssueWidth micro-ops can ever be scheduled in a particular cycle.
259 // In practice, IssueWidth is useful to model any bottleneck between the
265 unsigned IssueWidth;
268 unsigned IssueWidth; global() member
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSyntacoreSCR1.td20 let IssueWidth = 1;

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