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Searched refs:DestReg (Results 1 – 25 of 139) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp63 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
83 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
110 assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && in emitLoadConstPool()
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
126 const DebugLoc &dl, Register DestReg, Registe in emitThumbRegPlusImmInReg() argument
189 emitThumbRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags) emitThumbRegPlusImmediate() argument
377 Register DestReg = MI.getOperand(0).getReg(); rewriteFrameIndex() local
402 Register DestReg = FrameReg; rewriteFrameIndex() local
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H A DThumb1InstrInfo.cpp44 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
50 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
54 !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
55 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
70 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
98 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
110 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
145 Register DestReg, int FI, in loadRegFromStackSlot() argument
150 (DestReg.isPhysical() && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
154 (DestReg.isPhysical() && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
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H A DThumb2InstrInfo.cpp135 Register DestReg = MI.getOperand(0).getReg(); in optimizeSelect() local
137 if (!DestReg.isVirtual()) in optimizeSelect()
141 get(ARM::t2CSEL), DestReg) in optimizeSelect()
153 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
157 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
211 Register DestReg, int FI, in loadRegFromStackSlot() argument
224 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
236 if (DestReg.isVirtual()) { in loadRegFromStackSlot()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp82 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
84 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
103 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
106 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
113 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
116 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
118 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
119 Src1Reg = DestReg; in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp437 Register DestReg, int FI, in loadRegFromStackSlot() argument
472 BuildMI(MBB, I, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
480 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
483 CSKY::CARRYRegClass.contains(DestReg)) { in copyPhysReg()
485 BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg) in copyPhysReg()
490 BuildMI(MBB, I, DL, get(CSKY::BTSTI16), DestReg) in copyPhysReg()
498 CSKY::GPRRegClass.contains(DestReg)) { in copyPhysReg()
501 BuildMI(MBB, I, DL, get(CSKY::MVC32), DestReg) in copyPhysReg()
504 assert(DestReg < CSKY::R16); in copyPhysReg()
505 assert(DestReg < CSKY::R8); in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp265 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion()
277 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg) in insertMaskedMerge()
284 .addReg(DestReg) in insertMaskedMerge()
301 MachineBasicBlock *MBB, Register DestReg, in doMaskedAtomicBinOpExpansion()
317 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in doMaskedAtomicBinOpExpansion()
330 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion()
346 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering, STI)), DestReg) in doMaskedAtomicBinOpExpansion()
358 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
363 .addReg(DestReg) in expandAtomicBinOp()
368 .addReg(DestReg) in expandAtomicBinOp()
240 Register DestReg = MI.getOperand(0).getReg(); doAtomicBinOpExpansion() local
276 insertMaskedMerge(const RISCVInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
302 Register DestReg = MI.getOperand(0).getReg(); doMaskedAtomicBinOpExpansion() local
441 Register DestReg = MI.getOperand(0).getReg(); expandAtomicMinMaxOp() local
543 tryToFoldBNEOnCmpXchgResult(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register DestReg,Register CmpValReg,Register MaskReg,MachineBasicBlock * & LoopHeadBNETarget) tryToFoldBNEOnCmpXchgResult() argument
606 Register DestReg = MI.getOperand(0).getReg(); expandAtomicCmpXchg() local
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H A DRISCVMoveMerger.cpp140 Register DestReg = SecondPair->Destination->getReg(); in findMatchingInst()
145 if ((RegPair.Destination->getReg() == DestReg)) in findMatchingInst()
151 if (!ModifiedRegUnits.available(DestReg) || in findMatchingInst()
152 !UsedRegUnits.available(DestReg) || in findMatchingInst()
160 (RegPair.Destination->getReg() == DestReg)) in findMatchingInst()
163 if (!ModifiedRegUnits.available(DestReg) || in findMatchingInst()
164 !UsedRegUnits.available(DestReg) || in findMatchingInst()
142 Register DestReg = SecondPair->Destination->getReg(); findMatchingInst() local
H A DRISCVMergeBaseOffset.cpp304 Register DestReg = Lo.getOperand(0).getReg(); in detectAndFoldOffset() local
309 if (!MRI->hasOneUse(DestReg)) in detectAndFoldOffset()
313 MachineInstr &Tail = *MRI->use_instr_begin(DestReg); in detectAndFoldOffset()
349 return foldLargeOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
356 return foldShiftedOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
364 Register DestReg = Lo.getOperand(0).getReg(); in foldIntoMemoryOps() local
381 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in foldIntoMemoryOps()
406 if (DestReg == UseMI.getOperand(0).getReg()) in foldIntoMemoryOps()
408 assert(DestReg == UseMI.getOperand(1).getReg() && in foldIntoMemoryOps()
437 if (MO.isReg() && MO.getReg() == DestReg) in foldIntoMemoryOps()
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H A DRISCVRegisterInfo.cpp175 const DebugLoc &DL, Register DestReg, in adjustReg() argument
180 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable()) in adjustReg()
198 Register ScratchReg = DestReg; in adjustReg()
199 if (DestReg == SrcReg) in adjustReg()
215 BuildMI(MBB, II, DL, TII->get(Opc), DestReg) in adjustReg()
220 BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg) in adjustReg()
224 SrcReg = DestReg; in adjustReg()
229 if (DestReg == SrcReg && Val == 0) in adjustReg()
235 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
253 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp86 void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
824 void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg, in emitLAInstSeq() argument
840 Out.emitInstruction(MCInstBuilder(Opc).addReg(DestReg).addExpr(LE), in emitLAInstSeq()
849 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addImm(0), in emitLAInstSeq()
855 .addReg(DestReg) in emitLAInstSeq()
861 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addExpr(LE), in emitLAInstSeq()
867 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
868 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
881 .addReg(DestReg == TmpReg ? TmpReg : LoongArch::R0) in emitLAInstSeq()
888 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addReg(TmpReg), in emitLAInstSeq()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp152 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
163 TII->get(Width == 32 ? LoongArch::LL_W : LoongArch::LL_D), DestReg) in doAtomicBinOpExpansion()
176 .addReg(DestReg) in doAtomicBinOpExpansion()
184 .addReg(DestReg) in doAtomicBinOpExpansion()
189 .addReg(DestReg) in doAtomicBinOpExpansion()
194 .addReg(DestReg) in doAtomicBinOpExpansion()
199 .addReg(DestReg) in doAtomicBinOpExpansion()
204 .addReg(DestReg) in doAtomicBinOpExpansion()
219 MachineBasicBlock *MBB, Register DestReg, in doAtomicBinOpExpansion()
233 BuildMI(MBB, DL, TII->get(LoongArch::XOR), DestReg) in insertMaskedMerge()
225 insertMaskedMerge(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
249 Register DestReg = MI.getOperand(0).getReg(); doMaskedAtomicBinOpExpansion() local
396 Register DestReg = MI.getOperand(0).getReg(); expandAtomicMinMaxOp() local
519 Register DestReg = MI.getOperand(0).getReg(); expandAtomicCmpXchg() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp407 Register DestReg = I->getOperand(0).getReg(); in searchALUInst()
419 if (Opnd.getReg() == DestReg) { in searchALUInst()
440 if (TRI->regsOverlap(DestReg, Opnd.getReg())) in searchALUInst()
565 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA()
570 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
587 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
589 if (DestReg != BaseReg) in optTwoAddrLEA()
594 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
406 Register DestReg = I->getOperand(0).getReg(); searchALUInst() local
564 Register DestReg = MI.getOperand(0).getReg(); optTwoAddrLEA() local
757 Register DestReg = Dest.getReg(); processInstrForSlow3OpLEA() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp180 bool emitCmp(unsigned DestReg, const CmpInst *CI);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
191 unsigned DestReg);
193 unsigned DestReg);
390 Register DestReg = createResultReg(RC); in materializeFP() local
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
393 return DestReg; in materializeFP()
396 Register DestReg = createResultReg(RC); in materializeFP() local
[all …]
H A DMipsSEInstrInfo.cpp85 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
119 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
123 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
125 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
127 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp440 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
454 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
455 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
457 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
462 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
463 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
465 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
467 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
475 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
478 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp264 Register DestReg = MI->getOperand(0).getReg(); in getAluKind() local
265 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
266 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
268 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
270 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
272 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
274 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
350 Register DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
357 MO.getReg() == DestReg) in AssignSlot()
363 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
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H A DAMDGPUMachineCFGStructurizer.cpp43 unsigned DestReg;
58 PHIInfoElementT *findPHIInfoElement(unsigned DestReg);
65 void addDest(unsigned DestReg, const DebugLoc &DL);
67 void deleteDef(unsigned DestReg);
68 void addSource(unsigned DestReg, unsigned SourceReg,
70 void removeSource(unsigned DestReg, unsigned SourceReg,
73 unsigned &DestReg);
75 unsigned getNumSources(unsigned DestReg);
112 return Info->DestReg; in phiInfoElementGetDest()
117 Info->DestReg = NewDef; in phiInfoElementSetDef()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp146 inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) { in build() argument
147 return BuildMI(MBB, II, DL, MCID, DestReg); in build()
149 inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) { in build() argument
150 return build(get(InstOpc), DestReg); in build()
264 Register DestReg = MI.getOperand(0).getReg(); in processLDQ() local
265 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
266 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
334 Register DestReg = MI.getOperand(0).getReg(); in processLDVM() local
352 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
354 build(VE::LVMir_m, DestReg) in processLDVM()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp77 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
80 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
84 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
87 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
88 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp33 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
150 Register DestReg, int FI, in loadRegFromStackSlot() argument
159 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
161 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp44 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
49 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
52 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
53 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
58 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
79 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
81 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
83 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
89 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
166 Register DestReg, int FrameIndex, in loadRegFromStackSlot() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp613 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction()
616 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
618 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
619 ActiveChains[DestReg] = G.get(); in scanInstruction()
626 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction()
631 if (DestReg != AccumReg) in scanInstruction()
646 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
648 if (DestReg != AccumReg) { in scanInstruction()
649 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
662 << printReg(DestReg, TR in scanInstruction()
614 Register DestReg = MI->getOperand(0).getReg(); scanInstruction() local
627 Register DestReg = MI->getOperand(0).getReg(); scanInstruction() local
[all...]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h383 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
387 .addReg(DestReg, RegState::Define); in BuildMI()
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
403 .addReg(DestReg, RegState::Define); in BuildMI()
415 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
422 .addReg(DestReg, RegState::Define); in BuildMI()
427 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
432 DestReg); in BuildMI()
433 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); in BuildMI()
438 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp64 Register DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
92 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
95 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
97 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
102 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp59 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
65 Register::isVirtualRegister(DestReg) in copyPhysReg()
66 ? MRI.getRegClass(DestReg) in copyPhysReg()
67 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
71 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()

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