Searched hist:"4 a33bea003144e217d8a3ae666f171dfc2e97bd6" (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/phy/xilinx/ |
| H A D | Makefile | 4a33bea003144e217d8a3ae666f171dfc2e97bd6 Mon Jun 29 14:00:53 CEST 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| H A D | Kconfig | 4a33bea003144e217d8a3ae666f171dfc2e97bd6 Mon Jun 29 14:00:53 CEST 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| H A D | phy-zynqmp.c | 4a33bea003144e217d8a3ae666f171dfc2e97bd6 Mon Jun 29 14:00:53 CEST 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| /linux/drivers/phy/ |
| H A D | Makefile | diff 4a33bea003144e217d8a3ae666f171dfc2e97bd6 Mon Jun 29 14:00:53 CEST 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| H A D | Kconfig | diff 4a33bea003144e217d8a3ae666f171dfc2e97bd6 Mon Jun 29 14:00:53 CEST 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| /linux/ |
| H A D | MAINTAINERS | diff 4a33bea003144e217d8a3ae666f171dfc2e97bd6 Mon Jun 29 14:00:53 CEST 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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