phy: add basic support for NXPs TJA1145 CAN transceiver

Add basic driver support for NXPs TJA1145 CAN transceiver which brings the
PHY up/down by switching to normal/standby mode using SPI commands.

phy: add basic support for NXPs TJA1145 CAN transceiver

Add basic driver support for NXPs TJA1145 CAN transceiver which brings the
PHY up/down by switching to normal/standby mode using SPI commands.

Tested-by: lee.lockhey@gmail.com
Reviewed-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
Link: https://patch.msgid.link/20260602-tja1145-support-v6-2-0e0ffc8ee63d@liebherr.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.

Introduce support for EcoNet PCIe PHY controllers found in EN751221
and EN7528 SoCs, these SoCs are not identical but are simila

phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.

Introduce support for EcoNet PCIe PHY controllers found in EN751221
and EN7528 SoCs, these SoCs are not identical but are similar, each
having one Gen1 port, and one Gen1/Gen2 port.

Co-developed-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
[cjd@cjdns.fr: add EN751221 support and refactor for clarity]
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://patch.msgid.link/20260425173642.406089-3-cjd@cjdns.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: Add driver for EyeQ5 Ethernet PHY wrapper

EyeQ5 embeds a system-controller called OLB. It features many unrelated
registers, and some of those are registers used to configure the
integration of

phy: Add driver for EyeQ5 Ethernet PHY wrapper

EyeQ5 embeds a system-controller called OLB. It features many unrelated
registers, and some of those are registers used to configure the
integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.

Wrap in a neat generic PHY provider, exposing two PHYs with standard
phy_init() / phy_set_mode() / phy_power_on() operations.

Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://patch.msgid.link/20260309-macb-phy-v9-1-5afd87d9db43@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: axiado: add Axiado eMMC PHY driver

It provides the required configurations for Axiado eMMC PHY driver for
HS200 mode.

Signed-off-by: SriNavmani A <srinavmani@axiado.com>
Co-developed-by: Prasa

phy: axiado: add Axiado eMMC PHY driver

It provides the required configurations for Axiado eMMC PHY driver for
HS200 mode.

Signed-off-by: SriNavmani A <srinavmani@axiado.com>
Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>
Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
Link: https://patch.msgid.link/20260504-axiado-ax3000-add-emmc-phy-driver-support-v3-2-3ab7eb45b0c5@axiado.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver

Create the eswin phy driver directory and add support for the
SATA PHY driver on the EIC7700 SoC platform.

Signed-off-by: Yulin Lu

phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver

Create the eswin phy driver directory and add support for the
SATA PHY driver on the EIC7700 SoC platform.

Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Link: https://patch.msgid.link/20260205082219.1521-1-luyulin@eswincomputing.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: usb: Add driver for Canaan K230 USB 2.0 PHY

Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
initialization and power management.

Add Kconfig/Makefile under drivers/phy/ca

phy: usb: Add driver for Canaan K230 USB 2.0 PHY

Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
initialization and power management.

Add Kconfig/Makefile under drivers/phy/canaan/.

Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
Link: https://patch.msgid.link/20260121145526.14672-4-jiayu.riscv@isrc.iscas.ac.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: Sort the subsystem Makefile

Makefile is supposed to be sorted alphabetically, sadly it has bitrotted
so fix that

Link: https://patch.msgid.link/20260223065743.395539-1-vkoul@kernel.org
Signed-

phy: Sort the subsystem Makefile

Makefile is supposed to be sorted alphabetically, sadly it has bitrotted
so fix that

Link: https://patch.msgid.link/20260223065743.395539-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: move spacemit pcie driver to its subfolder

Commit fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
created spacemit subfolder with usb driver while commit 57e920b92724
("phy: sp

phy: move spacemit pcie driver to its subfolder

Commit fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
created spacemit subfolder with usb driver while commit 57e920b92724
("phy: spacemit: Introduce PCIe/combo PHY") added pcie driver in phy
folder. Move latter into spacemit subfolder and rename file to
phy-k1-pcie.c

Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260223064240.386617-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY

Kconfig option CONFIG_PHY_COMMON_PROPS, which builds
drivers/phy/phy-common-props.c, was intended to be selectable
independently of CO

phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY

Kconfig option CONFIG_PHY_COMMON_PROPS, which builds
drivers/phy/phy-common-props.c, was intended to be selectable
independently of CONFIG_GENERIC_PHY. Yet it lives in drivers/phy/, which
is entered by the Makefile only if CONFIG_GENERIC_PHY is set.

Allow the Makefile to enter one level deeper, but stop at drivers/phy/
if CONFIG_GENERIC_PHY is unselected (i.e. do not enter vendor folders).
The other stuff from drivers/phy/Makefile except for CONFIG_PHY_COMMON_PROPS,
like CONFIG_PHY_NXP_PTN3222, all depends on CONFIG_GENERIC_PHY.

Fixes: e7556b59ba65 ("phy: add phy_get_rx_polarity() and phy_get_tx_polarity()")
Closes: https://lore.kernel.org/lkml/43ea0202-891d-4582-980b-5cb557b41114@linux.ibm.com/
Reported-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
Debugged-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
Link: https://patch.msgid.link/20260123110600.3118561-1-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: Add Google Tensor SoC USB PHY driver

Support the USB PHY found on Google Tensor G5 (Laguna). This
particular USB PHY supports both high-speed and super-speed
operations, and is integrated with

phy: Add Google Tensor SoC USB PHY driver

Support the USB PHY found on Google Tensor G5 (Laguna). This
particular USB PHY supports both high-speed and super-speed
operations, and is integrated with the SNPS DWC3 controller that's
also on the SoC. This initial patch specifically adds functionality
for high-speed.

Co-developed-by: Joy Chakraborty <joychakr@google.com>
Signed-off-by: Joy Chakraborty <joychakr@google.com>
Co-developed-by: Naveen Kumar <mnkumar@google.com>
Signed-off-by: Naveen Kumar <mnkumar@google.com>
Signed-off-by: Roy Luo <royluo@google.com>
Link: https://patch.msgid.link/20251227-phyb4-v10-2-e8caf6b93fe7@google.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Merge tag 'phy_common_properties' into next

phy common properties

Vladimir Oltean <vladimir.oltean@nxp.com> wrote:

Introduce "rx-polarity" and "tx-polarity" device tree properties with
Kunit tests

phy: add phy_get_rx_polarity() and phy_get_tx_polarity()

Add helpers in the generic PHY folder which can be used using 'select
PHY_COMMON_PROPS' from Kconfig, without otherwise needing to
enable GEN

phy: add phy_get_rx_polarity() and phy_get_tx_polarity()

Add helpers in the generic PHY folder which can be used using 'select
PHY_COMMON_PROPS' from Kconfig, without otherwise needing to
enable GENERIC_PHY.

These helpers need to deal with the slight messiness of the fact that
the polarity properties are arrays per protocol, and with the fact that
there is no default value mandated by the standard properties, all
default values depend on driver and protocol (PHY_POL_NORMAL may be a
good default for SGMII, whereas PHY_POL_AUTO may be a good default for
PCIe).

Push the supported mask of polarities to these helpers, to simplify
drivers such that they don't need to validate what's in the device tree
(or other firmware description).

Add a KUnit test suite to make sure that the API produces the expected
results. The fact that we use fwnode structures means we can validate
with software nodes, and as opposed to the device_property API, we can
bypass the need to have a device structure.

Co-developed-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20260111093940.975359-6-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: spacemit: support K1 USB2.0 PHY controller

The SpacemiT K1 SoC includes three USB ports:

- One USB2.0 OTG port
- One USB2.0 host-only port
- One USB3.0 port with an integrated USB2.0 DRD inter

phy: spacemit: support K1 USB2.0 PHY controller

The SpacemiT K1 SoC includes three USB ports:

- One USB2.0 OTG port
- One USB2.0 host-only port
- One USB3.0 port with an integrated USB2.0 DRD interface

Each of these ports is connected to a USB2.0 PHY responsible for USB2
transmission.

This commit adds support for the SpacemiT K1 USB2.0 PHY, which is
compliant with the USB 2.0 specification and supports both 8-bit 60MHz
and 16-bit 30MHz parallel interfaces.

Signed-off-by: Ze Huang <huang.ze@linux.dev>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: apple: Add Apple Type-C PHY

The Apple Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x,
USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon SoCs.
The PHY handles muxing betwe

phy: apple: Add Apple Type-C PHY

The Apple Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x,
USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon SoCs.
The PHY handles muxing between these different protocols and also provides
the reset controller for the attached dwc3 USB controller.

There is no documentation available for this PHY and the entire sequence
of MMIO pokes has been figured out by tracing all MMIO access of Apple's
driver under a thin hypervisor and correlating the register reads/writes
to their kernel's debug output to find their names. Deviations from this
sequence generally results in the port not working or, especially when
the mode is switched to USB4 or Thunderbolt, to some watchdog resetting
the entire SoC.

This initial commit already introduces support for Display Port and
USB4/Thunderbolt but the drivers for these are not ready. We cannot
control the alternate mode negotiation and are stuck with whatever Apple's
firmware decides such that any DisplayPort or USB4/Thunderbolt device will
result in a correctly setup PHY but not be usable until the other drivers
are upstreamed as well.

Co-developed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
Co-developed-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> # for reset controller
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Sven Peter <sven@kernel.org>
Link: https://patch.msgid.link/20251214-b4-atcphy-v3-3-ba82b20e9459@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: spacemit: Introduce PCIe/combo PHY

Introduce a driver that supports three PHYs found on the SpacemiT
K1 SoC. The first PHY is a combo PHY that can be configured for
use for either USB 3 or PCI

phy: spacemit: Introduce PCIe/combo PHY

Introduce a driver that supports three PHYs found on the SpacemiT
K1 SoC. The first PHY is a combo PHY that can be configured for
use for either USB 3 or PCIe. The other two PHYs support PCIe
only.

All three PHYs must be programmed with an 8 bit receiver termination
value, which must be determined dynamically. Only the combo PHY is
able to determine this value. The combo PHY performs a special
calibration step at probe time to discover this, and that value is
used to program each PHY that operates in PCIe mode. The combo
PHY must therefore be probed before either of the PCIe-only PHYs
will be used.

Each PHY has an internal PLL driven from an external oscillator.
This PLL started when the PHY is first initialized, and stays
on thereafter.

During normal operation, the USB or PCIe driver using the PHY must
ensure (other) clocks and resets are set up properly.

However PCIe mode clocks are enabled and resets are de-asserted
temporarily by this driver to perform the calibration step on the
combo PHY.

Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20251218151235.454997-4-elder@riscstar.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: sophgo: Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X

Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X. Currently
this driver does not support OTG mode as lack of document.

Signed-off-by: Ino

phy: sophgo: Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X

Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X. Currently
this driver does not support OTG mode as lack of document.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250708063038.497473-3-inochiama@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory

As not only Qualcomm, but also Samsung is using the Synopsys eUSB2 IP
(albeit with a different register layout) in their newer SoCs, mov

phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory

As not only Qualcomm, but also Samsung is using the Synopsys eUSB2 IP
(albeit with a different register layout) in their newer SoCs, move the
driver out of its vendor sub-directory and rename it to phy-snps-eusb2.

Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250504144527.1723980-4-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: add NXP PTN3222 eUSB2 to USB2 redriver

The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs
translation between eUSB2 and USB2 signalling schemes. It supports all
three data

phy: add NXP PTN3222 eUSB2 to USB2 redriver

The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs
translation between eUSB2 and USB2 signalling schemes. It supports all
three data rates: Low Speed, Full Speed and High Speed.

The reset state enables autonegotiation of the PHY role and of the data
rate, so no additional programming is required.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Konrad Dybcio <konradybcio@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Tested-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-2-4c6d8535cf6c@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY

Nuvoton MA35 SoCs support DWC2 USB controller.
Add the driver to drive the USB 2.0 PHY transceivers.

Signed-off-by: Hui-Ping Chen <

phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY

Nuvoton MA35 SoCs support DWC2 USB controller.
Add the driver to drive the USB 2.0 PHY transceivers.

Signed-off-by: Hui-Ping Chen <hpchen0nvt@gmail.com>
Link: https://lore.kernel.org/r/20240805030356.14565-3-hpchen0nvt@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: airoha: Add PCIe PHY driver for EN7581 SoC.

Introduce support for Airoha PCIe PHY controller available in EN7581
SoC.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabo

phy: airoha: Add PCIe PHY driver for EN7581 SoC.

Introduce support for Airoha PCIe PHY controller available in EN7581
SoC.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20ac99aa8628d97778594f606681db7f868f24fe.1718485860.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: realtek: usb: add new driver for the Realtek RTD SoC USB 2.0 PHY

Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB
controller. Added the driver to drive the USB 2.0 PHY transceiv

phy: realtek: usb: add new driver for the Realtek RTD SoC USB 2.0 PHY

Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB
controller. Added the driver to drive the USB 2.0 PHY transceivers.

Note: New driver,remove the port status notification on legacy USB PHY.
Use the generic PHY to notify the usb device connect and disconnect.
To avoid using these PHYs would require describing the very same
PHY using both the generic "phy" property and the deprecated "usb-phy"
property.

Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
Link: https://lore.kernel.org/r/20231213031203.4911-2-stanley_chang@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Revert "phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY"

This reverts commit 134e6d25f6bd06071e5aac0a7eefcea6f7713955.

The recently added Realtek PHY drivers depend on the new port st

Revert "phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY"

This reverts commit 134e6d25f6bd06071e5aac0a7eefcea6f7713955.

The recently added Realtek PHY drivers depend on the new port status
notification mechanism which was built on the deprecated USB PHY
implementation and devicetree binding.

Specifically, using these PHYs would require describing the very same
PHY using both the generic "phy" property and the deprecated "usb-phy"
property which is clearly wrong.

We should not be building new functionality on top of the legacy USB PHY
implementation even if it is currently stuck in some kind of
transitional limbo.

Revert the new Realtek PHY drivers for now so that the port status
notification interface can be reverted and replaced.

Fixes: 134e6d25f6bd ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY")
Cc: stable@vger.kernel.org # 6.6
Cc: Stanley Chang <stanley_chang@realtek.com>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20231106110654.31090-3-johan+linaro@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Merge tag 'phy-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
"As usual a couple of new drivers, a bunch of new device support and
few u

Merge tag 'phy-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
"As usual a couple of new drivers, a bunch of new device support and
few updates to existing drivers

New Support:
- Starfive dphy rx, JH7110 usb and pcie support
- Rockchip rv1126 inno-dsi phy, rk3588 usb and pcie support
- Qualcomm sa8775p PCIe support, M31 USB PHY driver
- Samsung Exynos850 usb support

Updates:
- Mediatek dsi driver clock updates
- Qualcomm sm8150 combo phy with reworking of qmp pcie driver
- Xilinx zynqmp runtime PM support"

* tag 'phy-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (83 commits)
phy: exynos5-usbdrd: Add Exynos850 support
phy: exynos5-usbdrd: Add 26MHz ref clk support
phy: exynos5-usbdrd: Make it possible to pass custom phy ops
dt-bindings: phy: samsung,usb3-drd-phy: Add Exynos850 support
phy: qcom-qmp-combo: fix clock probing
phy: qcom-qmp-pcie: support SM8150 PCIe QMP PHYs
phy: qcom-qmp-pcie: populate offsets configuration
phy: qcom-qmp-pcie: simplify clock handling
phy: qcom-qmp-pcie: keep offset tables sorted
phy: qcom-qmp-pcie: drop ln_shrd from v5_20 config
dt-bindings: phy: qcom,qmp-pcie: describe SM8150 PCIe PHYs
dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml
phy: fsl-imx8mq-usb: add dev_err_probe if getting vbus failed
phy: qcom: Introduce M31 USB PHY driver
dt-bindings: phy: qcom,m31: Document qcom,m31 USB phy
phy: rockchip: inno-dsidphy: Add rv1126 support
dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126
dt-bindings: phy: mediatek,tphy: allow simple nodename pattern
phy: amlogic: meson-g12a-usb2: fix Wvoid-pointer-to-enum-cast warning
phy: marvell pxa-usb: fix Wvoid-pointer-to-enum-cast warning
...

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phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY

Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB
controller. Added the driver to drive the USB 2.0 PHY transceivers.

Si

phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY

Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB
controller. Added the driver to drive the USB 2.0 PHY transceivers.

Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
Link: https://lore.kernel.org/r/20230725033318.8361-2-stanley_chang@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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phy: starfive: Add JH7110 USB 2.0 PHY driver

Add Starfive JH7110 SoC USB 2.0 PHY driver support.
USB 2.0 PHY default connect to Cadence USB controller.

Signed-off-by: Minda Chen <minda.chen@starfiv

phy: starfive: Add JH7110 USB 2.0 PHY driver

Add Starfive JH7110 SoC USB 2.0 PHY driver support.
USB 2.0 PHY default connect to Cadence USB controller.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230629075115.11934-4-minda.chen@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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