Changes in Makefile

e5a9c1c917b59a4aff066b9f317501834c6d5af2 - phy: add basic support for NXPs TJA1145 CAN transceiver

Tue, 02 Jun 2026 10:25:38 +0200

phy: add basic support for NXPs TJA1145 CAN transceiverAdd basic driver support for NXPs TJA1145 CAN transceiver which brings thePHY up/down by switching to normal/standby mode using SPI commands.Tested-by: lee.lockhey@gmail.comReviewed-by: Marc Kleine-Budde Signed-off-by: Dimitri Fedrau Link: https://patch.msgid.link/20260602-tja1145-support-v6-2-0e0ffc8ee63d@liebherr.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

da1af49257591190ad6521abb3198f1f40420407 - phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.

Sat, 25 Apr 2026 19:36:42 +0200

phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.Introduce support for EcoNet PCIe PHY controllers found in EN751221and EN7528 SoCs, these SoCs are not identical but are similar, eachhaving one Gen1 port, and one Gen1/Gen2 port.Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef [cjd@cjdns.fr: add EN751221 support and refactor for clarity]Signed-off-by: Caleb James DeLisle Link: https://patch.msgid.link/20260425173642.406089-3-cjd@cjdns.frSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

b6e33443876d0ca7e93cf949455e3c1a1a0aae24 - phy: Add driver for EyeQ5 Ethernet PHY wrapper

Mon, 09 Mar 2026 15:37:34 +0100

phy: Add driver for EyeQ5 Ethernet PHY wrapperEyeQ5 embeds a system-controller called OLB. It features many unrelatedregisters, and some of those are registers used to configure theintegration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.Wrap in a neat generic PHY provider, exposing two PHYs with standardphy_init() / phy_set_mode() / phy_power_on() operations.Reviewed-by: Luca Ceresoli Signed-off-by: Théo Lebrun Reviewed-by: Vladimir Oltean Link: https://patch.msgid.link/20260309-macb-phy-v9-1-5afd87d9db43@bootlin.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

9e7dfa4bcd4e2c3541c4ee954ea5e66edab94d3f - phy: axiado: add Axiado eMMC PHY driver

Mon, 04 May 2026 03:38:33 +0200

phy: axiado: add Axiado eMMC PHY driverIt provides the required configurations for Axiado eMMC PHY driver forHS200 mode.Signed-off-by: SriNavmani A Co-developed-by: Prasad Bolisetty Signed-off-by: Prasad Bolisetty Signed-off-by: Tzu-Hao Wei Link: https://patch.msgid.link/20260504-axiado-ax3000-add-emmc-phy-driver-support-v3-2-3ab7eb45b0c5@axiado.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

67ee9ccaa34a11c317411bb8e7d305d93d0b4111 - phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver

Thu, 05 Feb 2026 09:22:19 +0100

phy: eswin: Create eswin directory and add EIC7700 SATA PHY driverCreate the eswin phy driver directory and add support for theSATA PHY driver on the EIC7700 SoC platform.Signed-off-by: Yulin Lu Link: https://patch.msgid.link/20260205082219.1521-1-luyulin@eswincomputing.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

8787fa1da603e9e51efff11841e97b5d374aef34 - phy: usb: Add driver for Canaan K230 USB 2.0 PHY

Wed, 21 Jan 2026 15:55:24 +0100

phy: usb: Add driver for Canaan K230 USB 2.0 PHYAdd driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHYinitialization and power management.Add Kconfig/Makefile under drivers/phy/canaan/.Signed-off-by: Jiayu Du Link: https://patch.msgid.link/20260121145526.14672-4-jiayu.riscv@isrc.iscas.ac.cnSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

d8f0ef2aebaa90c0155e266c1fdd6fa2aef44bb1 - phy: Sort the subsystem Makefile

Mon, 23 Feb 2026 07:57:43 +0100

phy: Sort the subsystem MakefileMakefile is supposed to be sorted alphabetically, sadly it has bitrottedso fix thatLink: https://patch.msgid.link/20260223065743.395539-1-vkoul@kernel.orgSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

75fb1a33f9ac4c9730e61bb19aaaab02023a99b2 - phy: move spacemit pcie driver to its subfolder

Mon, 23 Feb 2026 07:42:39 +0100

phy: move spacemit pcie driver to its subfolderCommit fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")created spacemit subfolder with usb driver while commit 57e920b92724("phy: spacemit: Introduce PCIe/combo PHY") added pcie driver in phyfolder. Move latter into spacemit subfolder and rename file tophy-k1-pcie.cReviewed-by: Alex Elder Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260223064240.386617-1-vkoul@kernel.orgSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

3ddcd24b4d8454b2b9b2d013a0d61986ae8bbbe7 - phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY

Fri, 23 Jan 2026 12:06:00 +0100

phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHYKconfig option CONFIG_PHY_COMMON_PROPS, which buildsdrivers/phy/phy-common-props.c, was intended to be selectableindependently of CONFIG_GENERIC_PHY. Yet it lives in drivers/phy/, whichis entered by the Makefile only if CONFIG_GENERIC_PHY is set.Allow the Makefile to enter one level deeper, but stop at drivers/phy/if CONFIG_GENERIC_PHY is unselected (i.e. do not enter vendor folders).The other stuff from drivers/phy/Makefile except for CONFIG_PHY_COMMON_PROPS,like CONFIG_PHY_NXP_PTN3222, all depends on CONFIG_GENERIC_PHY.Fixes: e7556b59ba65 ("phy: add phy_get_rx_polarity() and phy_get_tx_polarity()")Closes: https://lore.kernel.org/lkml/43ea0202-891d-4582-980b-5cb557b41114@linux.ibm.com/Reported-by: Venkat Rao Bagalkote Debugged-by: Christophe Leroy (CS GROUP) Signed-off-by: Vladimir Oltean Reviewed-by: Christophe Leroy (CS GROUP) Tested-by: Venkat Rao Bagalkote Link: https://patch.msgid.link/20260123110600.3118561-1-vladimir.oltean@nxp.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

cbce66669c82ee9ae0e26523c0fcd3c721fcfe85 - phy: Add Google Tensor SoC USB PHY driver

Sat, 27 Dec 2025 01:53:29 +0100

phy: Add Google Tensor SoC USB PHY driverSupport the USB PHY found on Google Tensor G5 (Laguna). Thisparticular USB PHY supports both high-speed and super-speedoperations, and is integrated with the SNPS DWC3 controller that'salso on the SoC. This initial patch specifically adds functionalityfor high-speed.Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo Link: https://patch.msgid.link/20251227-phyb4-v10-2-e8caf6b93fe7@google.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

a699808928937000e550a7cd5355db93ef99e236 - Merge tag 'phy_common_properties' into next

Wed, 14 Jan 2026 14:22:57 +0100

Merge tag 'phy_common_properties' into nextphy common propertiesVladimir Oltean wrote:Introduce "rx-polarity" and "tx-polarity" device tree properties withKunit tests List of files: /linux/drivers/phy/Makefile

e7556b59ba65179612bce3fa56bb53d1b4fb20db - phy: add phy_get_rx_polarity() and phy_get_tx_polarity()

Sun, 11 Jan 2026 10:39:34 +0100

phy: add phy_get_rx_polarity() and phy_get_tx_polarity()Add helpers in the generic PHY folder which can be used using 'selectPHY_COMMON_PROPS' from Kconfig, without otherwise needing toenable GENERIC_PHY.These helpers need to deal with the slight messiness of the fact thatthe polarity properties are arrays per protocol, and with the fact thatthere is no default value mandated by the standard properties, alldefault values depend on driver and protocol (PHY_POL_NORMAL may be agood default for SGMII, whereas PHY_POL_AUTO may be a good default forPCIe).Push the supported mask of polarities to these helpers, to simplifydrivers such that they don't need to validate what's in the device tree(or other firmware description).Add a KUnit test suite to make sure that the API produces the expectedresults. The fact that we use fwnode structures means we can validatewith software nodes, and as opposed to the device_property API, we canbypass the need to have a device structure.Co-developed-by: Bjørn Mork Signed-off-by: Bjørn Mork Signed-off-by: Vladimir Oltean Link: https://patch.msgid.link/20260111093940.975359-6-vladimir.oltean@nxp.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

fe4bc1a08638309b6be1af37210930b856908eb7 - phy: spacemit: support K1 USB2.0 PHY controller

Fri, 17 Oct 2025 16:49:53 +0200

phy: spacemit: support K1 USB2.0 PHY controllerThe SpacemiT K1 SoC includes three USB ports:- One USB2.0 OTG port- One USB2.0 host-only port- One USB3.0 port with an integrated USB2.0 DRD interfaceEach of these ports is connected to a USB2.0 PHY responsible for USB2transmission.This commit adds support for the SpacemiT K1 USB2.0 PHY, which iscompliant with the USB 2.0 specification and supports both 8-bit 60MHzand 16-bit 30MHz parallel interfaces.Signed-off-by: Ze Huang Tested-by: Aurelien Jarno Tested-by: Junzhong Pan Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.devSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

8e98ca1e74db2ae051c9b545d42b879efa5a2f6c - phy: apple: Add Apple Type-C PHY

Sun, 14 Dec 2025 12:51:36 +0100

phy: apple: Add Apple Type-C PHYThe Apple Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x,USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon SoCs.The PHY handles muxing between these different protocols and also providesthe reset controller for the attached dwc3 USB controller.There is no documentation available for this PHY and the entire sequenceof MMIO pokes has been figured out by tracing all MMIO access of Apple'sdriver under a thin hypervisor and correlating the register reads/writesto their kernel's debug output to find their names. Deviations from thissequence generally results in the port not working or, especially whenthe mode is switched to USB4 or Thunderbolt, to some watchdog resettingthe entire SoC.This initial commit already introduces support for Display Port andUSB4/Thunderbolt but the drivers for these are not ready. We cannotcontrol the alternate mode negotiation and are stuck with whatever Apple'sfirmware decides such that any DisplayPort or USB4/Thunderbolt device willresult in a correctly setup PHY but not be usable until the other driversare upstreamed as well.Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Co-developed-by: Hector Martin Signed-off-by: Hector Martin Reviewed-by: Philipp Zabel # for reset controllerReviewed-by: Neal Gompa Signed-off-by: Sven Peter Link: https://patch.msgid.link/20251214-b4-atcphy-v3-3-ba82b20e9459@kernel.orgSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

57e920b92724dd568526990c04e79ed54241c5fc - phy: spacemit: Introduce PCIe/combo PHY

Thu, 18 Dec 2025 16:12:29 +0100

phy: spacemit: Introduce PCIe/combo PHYIntroduce a driver that supports three PHYs found on the SpacemiTK1 SoC. The first PHY is a combo PHY that can be configured foruse for either USB 3 or PCIe. The other two PHYs support PCIeonly.All three PHYs must be programmed with an 8 bit receiver terminationvalue, which must be determined dynamically. Only the combo PHY isable to determine this value. The combo PHY performs a specialcalibration step at probe time to discover this, and that value isused to program each PHY that operates in PCIe mode. The comboPHY must therefore be probed before either of the PCIe-only PHYswill be used.Each PHY has an internal PLL driven from an external oscillator.This PLL started when the PHY is first initialized, and stayson thereafter.During normal operation, the USB or PCIe driver using the PHY mustensure (other) clocks and resets are set up properly.However PCIe mode clocks are enabled and resets are de-assertedtemporarily by this driver to perform the calibration step on thecombo PHY.Tested-by: Junzhong Pan Signed-off-by: Alex Elder Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]Tested-by: Yixun Lan Link: https://patch.msgid.link/20251218151235.454997-4-elder@riscstar.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

f0c6d776f74d1d8bda94f6f042b2919bcd615280 - phy: sophgo: Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X

Tue, 08 Jul 2025 08:30:37 +0200

phy: sophgo: Add USB 2.0 PHY driver for Sophgo CV18XX/SG200XAdd USB 2.0 PHY driver for Sophgo CV18XX/SG200X. Currentlythis driver does not support OTG mode as lack of document.Signed-off-by: Inochi Amaoto Tested-by: Alexander Sverdlin Link: https://lore.kernel.org/r/20250708063038.497473-3-inochiama@gmail.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

8d3b5f6375466ffcd2cd98a0c84d31295470fe9d - phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory

Sun, 04 May 2025 16:45:20 +0200

phy: move phy-qcom-snps-eusb2 out of its vendor sub-directoryAs not only Qualcomm, but also Samsung is using the Synopsys eUSB2 IP(albeit with a different register layout) in their newer SoCs, move thedriver out of its vendor sub-directory and rename it to phy-snps-eusb2.Suggested-by: Krzysztof Kozlowski Signed-off-by: Ivaylo Ivanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504144527.1723980-4-ivo.ivanov.ivanov1@gmail.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

c9be539e11f0bf1665c03108d3b7881a5d67ae48 - phy: add NXP PTN3222 eUSB2 to USB2 redriver

Fri, 30 Aug 2024 10:20:46 +0200

phy: add NXP PTN3222 eUSB2 to USB2 redriverThe NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performstranslation between eUSB2 and USB2 signalling schemes. It supports allthree data rates: Low Speed, Full Speed and High Speed.The reset state enables autonegotiation of the PHY role and of the datarate, so no additional programming is required.Reviewed-by: Neil Armstrong Tested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephan Gerhold Tested-by: Stephan Gerhold Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-2-4c6d8535cf6c@linaro.orgSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

b48baf69db9725aa5ddde52d98cd7b5517ddd9eb - phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY

Mon, 05 Aug 2024 05:03:56 +0200

phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHYNuvoton MA35 SoCs support DWC2 USB controller.Add the driver to drive the USB 2.0 PHY transceivers.Signed-off-by: Hui-Ping Chen Link: https://lore.kernel.org/r/20240805030356.14565-3-hpchen0nvt@gmail.comSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile

d7d2818b93837def4a33f92da2e64c3a2752c47e - phy: airoha: Add PCIe PHY driver for EN7581 SoC.

Sat, 15 Jun 2024 23:15:42 +0200

phy: airoha: Add PCIe PHY driver for EN7581 SoC.Introduce support for Airoha PCIe PHY controller available in EN7581SoC.Reviewed-by: AngeloGioacchino Del Regno Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/20ac99aa8628d97778594f606681db7f868f24fe.1718485860.git.lorenzo@kernel.orgSigned-off-by: Vinod Koul List of files: /linux/drivers/phy/Makefile