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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaX86.cpp1 //===------ SemaX86.cpp ---------- X86 target-specific routines -----------===//
9 // This file implements semantic analysis functions specific to X86.
36 case X86::BI__builtin_ia32_vcvttsd2si32: in CheckBuiltinRoundingOrSAE()
37 case X86::BI__builtin_ia32_vcvttsd2si64: in CheckBuiltinRoundingOrSAE()
38 case X86::BI__builtin_ia32_vcvttsd2usi32: in CheckBuiltinRoundingOrSAE()
39 case X86::BI__builtin_ia32_vcvttsd2usi64: in CheckBuiltinRoundingOrSAE()
40 case X86::BI__builtin_ia32_vcvttss2si32: in CheckBuiltinRoundingOrSAE()
41 case X86::BI__builtin_ia32_vcvttss2si64: in CheckBuiltinRoundingOrSAE()
42 case X86::BI__builtin_ia32_vcvttss2usi32: in CheckBuiltinRoundingOrSAE()
43 case X86::BI__builtin_ia32_vcvttss2usi64: in CheckBuiltinRoundingOrSAE()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
52 #define DEBUG_TYPE "x86-instr-info"
64 " fuse, but the X86 backend currently can't"),
86 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
87 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
88 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
89 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
90 X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)), in X86InstrInfo()
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H A DX86FixupInstTuning.cpp24 #include "X86.h"
34 #define DEBUG_TYPE "x86-fixup-inst-tuning"
45 StringRef getPassName() const override { return "X86 Fixup Inst Tuning"; } in getPassName()
228 case X86::VPERMILPDri: in processInstruction()
229 return ProcessVPERMILPDri(X86::VSHUFPDrri); in processInstruction()
230 case X86::VPERMILPDYri: in processInstruction()
231 return ProcessVPERMILPDri(X86::VSHUFPDYrri); in processInstruction()
232 case X86::VPERMILPDZ128ri: in processInstruction()
233 return ProcessVPERMILPDri(X86::VSHUFPDZ128rri); in processInstruction()
234 case X86::VPERMILPDZ256ri: in processInstruction()
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H A DX86FloatingPoint.cpp25 #include "X86.h"
51 #define DEBUG_TYPE "x86-codegen"
83 StringRef getPassName() const override { return "X86 FP Stackifier"; } in getPassName()
130 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
131 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
132 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
194 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
201 /// getSTReg - Return the X86::ST(i) register which contains the specified
204 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
240 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
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H A DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
9 // This file contains the X86 memory folding tables.
30 { X86::VANDNPDZ128rr, X86::VANDNPSZ128rmb, TB_BCAST_SS },
31 { X86::VANDNPDZ256rr, X86::VANDNPSZ256rmb, TB_BCAST_SS },
32 { X86::VANDNPDZrr, X86::VANDNPSZrmb, TB_BCAST_SS },
33 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rmb, TB_BCAST_SD },
34 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rmb, TB_BCAST_SD },
35 { X86::VANDNPSZrr, X86::VANDNPDZrmb, TB_BCAST_SD },
36 { X86::VANDPDZ128rr, X86::VANDPSZ128rmb, TB_BCAST_SS },
37 { X86::VANDPDZ256rr, X86::VANDPSZ256rmb, TB_BCAST_SS },
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H A DX86FixupVectorConstants.cpp18 #include "X86.h"
27 #define DEBUG_TYPE "x86-fixup-vector-constants"
39 return "X86 Fixup Vector Constants"; in getPassName()
359 assert(MI.getNumOperands() >= (OperandNo + X86::AddrNumOperands) && in processInstruction()
361 if (auto *C = X86::getConstantFromPool(MI, OperandNo)) { in processInstruction()
373 MI.getOperand(OperandNo + X86::AddrDisp).setIndex(NewCPI); in processInstruction()
393 case X86::MOVAPDrm: in processInstruction()
394 case X86::MOVAPSrm: in processInstruction()
395 case X86::MOVUPDrm: in processInstruction()
396 case X86::MOVUPSrm: in processInstruction()
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H A DX86AvoidStoreForwardingBlocks.cpp36 #include "X86.h"
55 #define DEBUG_TYPE "x86-avoid-SFB"
58 "x86-disable-avoid-SFB", cl::Hidden,
59 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false));
62 "x86-sfb-inspection-limit",
63 cl::desc("X86: Number of instructions backward to "
77 return "X86 Avoid Store Forwarding Blocks"; in getPassName()
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
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H A DX86DomainReassignment.cpp15 #include "X86.h"
33 #define DEBUG_TYPE "x86-domain-reassignment"
38 "disable-x86-domain-reassignment", cl::Hidden,
39 cl::desc("X86: Disable Virtual Register Reassignment."), cl::init(false));
45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
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H A DX86ExpandPseudo.cpp15 #include "X86.h"
30 #define DEBUG_TYPE "x86-pseudo"
31 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
60 return "X86 pseudo instruction expansion pass"; in getPassName()
76 /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
107 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
108 .addReg(X86::RIP) in INITIALIZE_PASS()
114 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
116 .addReg(X86::R11); in INITIALIZE_PASS()
122 if (!MBB->isLiveIn(X86::EFLAGS)) in INITIALIZE_PASS()
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H A DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
335 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32; in getRetOpcode()
374 case X86::TAILJMPr: in convertTailJumpOpcode()
375 Opcode = X86::JMP32r; in convertTailJumpOpcode()
377 case X86::TAILJMPm: in convertTailJumpOpcode()
378 Opcode = X86::JMP32m; in convertTailJumpOpcode()
380 case X86::TAILJMPr64: in convertTailJumpOpcode()
381 Opcode = X86::JMP64r; in convertTailJumpOpcode()
383 case X86::TAILJMPm64: in convertTailJumpOpcode()
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H A DX86RegisterInfo.cpp1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // on X86.
45 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
69 FramePtr = Use64BitReg ? X86::RBP : X86::EBP; in X86RegisterInfo()
70 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
73 StackPtr = X86::ESP; in X86RegisterInfo()
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H A DX86InstructionSelector.cpp
H A DX86TargetTransformInfo.h1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
10 /// X86 target machine. It uses the target's detailed information to
42 X86::FeatureX86_64,
45 X86::FeatureNOPL,
46 X86::FeatureCX16,
47 X86::FeatureLAHFSAHF64,
50 X86::FeatureSSEUnalignedMem,
53 X86::TuningFast11ByteNOP,
54 X86::TuningFast15ByteNOP,
55 X86::TuningFastBEXTR,
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H A DX86FastISel.cpp1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
9 // This file defines the X86-specific support for the FastISel class. Much
15 #include "X86.h"
161 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
219 X86::AddrIndexReg); in addFullAddress()
225 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, in foldX86XALUIntrinsic()
245 X86::CondCode TmpCC; in foldX86XALUIntrinsic()
251 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break; in foldX86XALUIntrinsic()
253 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break; in foldX86XALUIntrinsic()
306 // We only handle legal types. For example, on x86-32 the instruction in isTypeLegal()
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H A DX86EvexToVex.cpp
H A DX86CompressEVEX.cpp41 #include "X86.h"
58 #define COMP_EVEX_NAME "x86-compress-evex"
89 if (Reg >= X86::XMM16 && Reg <= X86::XMM31) in usesExtendedRegister()
92 if (Reg >= X86::YMM16 && Reg <= X86::YMM31) in usesExtendedRegister()
121 case X86::VALIGNDZ128rri: in performCustomAdjustments()
122 case X86::VALIGNDZ128rmi: in performCustomAdjustments()
123 case X86::VALIGNQZ128rri: in performCustomAdjustments()
124 case X86::VALIGNQZ128rmi: { in performCustomAdjustments()
125 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
128 (Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4; in performCustomAdjustments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstPrinterCommon.cpp1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
33 bool IsCMPCCXADD = X86::isCMPCCXADD(Opc); in printCondCode()
34 bool IsCCMPOrCTEST = X86::isCCMPCC(Opc) || X86::isCTESTCC(Opc); in printCondCode()
139 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
140 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
141 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
142 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
143 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
144 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
145 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
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H A DX86IntelInstPrinter.cpp46 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
47 STI.hasFeature(X86::Is16Bit)) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrmi: case X86::CMPSDrri: in printVecCompareInstr()
75 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int: in printVecCompareInstr()
76 case X86::CMPSSrmi: case X86::CMPSSrri: in printVecCompareInstr()
77 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
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H A DX86ATTInstPrinter.cpp57 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
58 (STI.hasFeature(X86::Is64Bit))) { in printInst()
67 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
68 STI.hasFeature(X86::Is16Bit)) { in printInst()
92 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
93 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
94 case X86::CMPSDrmi: case X86::CMPSDrri: in printVecCompareInstr()
95 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int: in printVecCompareInstr()
96 case X86::CMPSSrmi: case X86::CMPSSrri: in printVecCompareInstr()
97 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int: in printVecCompareInstr()
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H A DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && Base.getReg() == 0 && in is16BitMemOperand()
94 return isMemOperand(MI, Op, X86::GR16RegClassID); in is16BitMemOperand()
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
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H A DX86BaseInfo.h1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
10 // the X86 target useful for the compiler back-end and the MC libraries.
25 namespace X86 {
75 // X86 specific condition code. These correspond to X86_*_COND in
98 // which can't be represented on x86 with a single condition. These
131 case X86::TEST16i16: in classifyFirstOpcodeInMacroFusion()
132 case X86::TEST16mr: in classifyFirstOpcodeInMacroFusion()
133 case X86::TEST16ri: in classifyFirstOpcodeInMacroFusion()
134 case X86::TEST16rr: in classifyFirstOpcodeInMacroFusion()
135 case X86::TEST32i32: in classifyFirstOpcodeInMacroFusion()
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/freebsd/crypto/openssl/fuzz/
H A Doids.txt10 OBJ_rsadsi="\x2A\x86\x48\x86\xF7\x0D"
11 OBJ_pkcs="\x2A\x86\x48\x86\xF7\x0D\x01"
12 OBJ_md2="\x2A\x86\x48\x86\xF7\x0D\x02\x02"
13 OBJ_md5="\x2A\x86\x48\x86\xF7\x0D\x02\x05"
14 OBJ_rc4="\x2A\x86\x48\x86\xF7\x0D\x03\x04"
15 OBJ_rsaEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x01"
16 OBJ_md2WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x02"
17 OBJ_md5WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x04"
18 OBJ_pbeWithMD2AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x01"
19 OBJ_pbeWithMD5AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x03"
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp10 /// X86.
15 #include "X86.h"
51 #define DEBUG_TYPE "X86-isel"
173 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
175 return &X86::GR8RegClass; in getRegClass()
177 return &X86::GR16RegClass; in getRegClass()
179 return &X86::GR32RegClass; in getRegClass()
181 return &X86::GR64RegClass; in getRegClass()
183 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
185 return STI.hasAVX512() ? &X86::FR16XRegClass : &X86::FR16RegClass; in getRegClass()
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/freebsd/sys/contrib/x86emu/
H A Dx86emu.c6 * Realmode X86 Emulator Library
182 push_word(emu, (uint16_t) emu->x86.R_FLG); in x86emu_intr_dispatch()
185 push_word(emu, emu->x86.R_CS); in x86emu_intr_dispatch()
186 emu->x86.R_CS = fetch_word(emu, 0, intno * 4 + 2); in x86emu_intr_dispatch()
187 push_word(emu, emu->x86.R_IP); in x86emu_intr_dispatch()
188 emu->x86.R_IP = fetch_word(emu, 0, intno * 4); in x86emu_intr_dispatch()
197 if (emu->x86.intr & INTR_SYNCH) { in x86emu_intr_handle()
198 intno = emu->x86.intno; in x86emu_intr_handle()
199 emu->x86.intr = 0; in x86emu_intr_handle()
215 emu->x86.intno = intrnum; in x86emu_intr_raise()
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/freebsd/sys/conf/
H A Dfiles.x865 # This file contains all the x86 devices and such that are
19 cddl/dev/fbt/x86/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
20 cddl/dev/dtrace/x86/dis_tables.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}"
21 cddl/dev/dtrace/x86/instr_size.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}"
139 dev/hyperv/vmbus/x86/hyperv_x86.c optional hyperv
140 dev/hyperv/vmbus/x86/vmbus_x86.c optional hyperv
335 libkern/x86/crc32_sse42.c standard
338 # x86 shared code between IA32 and AMD64 architectures
340 x86/acpica/OsdEnvironment.c optional acpi
341 x86/acpica/acpi_apm.c optional acpi
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