Lines Matching full:x86
15 #include "X86.h"
30 #define DEBUG_TYPE "x86-pseudo"
31 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
60 return "X86 pseudo instruction expansion pass"; in getPassName()
76 /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
107 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
108 .addReg(X86::RIP) in INITIALIZE_PASS()
114 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
116 .addReg(X86::R11); in INITIALIZE_PASS()
122 if (!MBB->isLiveIn(X86::EFLAGS)) in INITIALIZE_PASS()
123 MBB->addLiveIn(X86::EFLAGS); in INITIALIZE_PASS()
128 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC); in INITIALIZE_PASS()
143 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
156 EmitCondJumpTarget(X86::COND_B, FirstTarget); in INITIALIZE_PASS()
163 EmitCondJumpTarget(X86::COND_B, FirstTarget); in INITIALIZE_PASS()
164 EmitCondJumpTarget(X86::COND_E, FirstTarget + 1); in INITIALIZE_PASS()
171 EmitCondJump(X86::COND_B, ThenMBB); in INITIALIZE_PASS()
172 EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2)); in INITIALIZE_PASS()
185 BuildMI(P.first, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
201 if (MI.getOpcode() == X86::CALL64m_RVMARKER) in expandCALL_RVMARKER()
202 Opc = X86::CALL64m; in expandCALL_RVMARKER()
203 else if (MI.getOpcode() == X86::CALL64r_RVMARKER) in expandCALL_RVMARKER()
204 Opc = X86::CALL64r; in expandCALL_RVMARKER()
205 else if (MI.getOpcode() == X86::CALL64pcrel32_RVMARKER) in expandCALL_RVMARKER()
206 Opc = X86::CALL64pcrel32; in expandCALL_RVMARKER()
216 TRI->regsOverlap(Op.getReg(), X86::RAX)) { in expandCALL_RVMARKER()
229 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI; in expandCALL_RVMARKER()
230 auto *Marker = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::MOV64rr)) in expandCALL_RVMARKER()
232 .addReg(X86::RAX) in expandCALL_RVMARKER()
241 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::CALL64pcrel32)) in expandCALL_RVMARKER()
244 .addReg(X86::RAX, in expandCALL_RVMARKER()
271 case X86::TCRETURNdi: in expandMI()
272 case X86::TCRETURNdicc: in expandMI()
273 case X86::TCRETURNri: in expandMI()
274 case X86::TCRETURNmi: in expandMI()
275 case X86::TCRETURNdi64: in expandMI()
276 case X86::TCRETURNdi64cc: in expandMI()
277 case X86::TCRETURNri64: in expandMI()
278 case X86::TCRETURNmi64: { in expandMI()
279 bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64; in expandMI()
281 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands in expandMI()
295 if (Opcode == X86::TCRETURNdicc || Opcode == X86::TCRETURNdi64cc) { in expandMI()
307 if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdicc || in expandMI()
308 Opcode == X86::TCRETURNdi64 || Opcode == X86::TCRETURNdi64cc) { in expandMI()
311 case X86::TCRETURNdi: in expandMI()
312 Op = X86::TAILJMPd; in expandMI()
314 case X86::TCRETURNdicc: in expandMI()
315 Op = X86::TAILJMPd_CC; in expandMI()
317 case X86::TCRETURNdi64cc: in expandMI()
321 Op = X86::TAILJMPd64_CC; in expandMI()
326 Op = X86::TAILJMPd64; in expandMI()
338 if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) { in expandMI()
342 } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) { in expandMI()
343 unsigned Op = (Opcode == X86::TCRETURNmi) in expandMI()
344 ? X86::TAILJMPm in expandMI()
345 : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64); in expandMI()
347 for (unsigned i = 0; i != X86::AddrNumOperands; ++i) in expandMI()
349 } else if (Opcode == X86::TCRETURNri64) { in expandMI()
352 TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64)) in expandMI()
356 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr)) in expandMI()
373 case X86::EH_RETURN: in expandMI()
374 case X86::EH_RETURN64: { in expandMI()
381 TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr) in expandMI()
386 case X86::IRET: { in expandMI()
391 unsigned RetOp = STI->is64Bit() ? X86::IRET64 : X86::IRET32; in expandMI()
395 RetOp = X86::UIRET; in expandMI()
400 case X86::RET: { in expandMI()
406 TII->get(STI->is64Bit() ? X86::RET64 : X86::RET32)); in expandMI()
409 TII->get(STI->is64Bit() ? X86::RETI64 : X86::RETI32)) in expandMI()
416 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define); in expandMI()
418 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX); in expandMI()
419 MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RET32)); in expandMI()
426 case X86::LCMPXCHG16B_SAVE_RBX: { in expandMI()
440 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, InArg.getReg(), false); in expandMI()
442 MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(X86::LCMPXCHG16B)); in expandMI()
447 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, in expandMI()
462 case X86::MASKPAIR16LOAD: { in expandMI()
463 int64_t Disp = MBBI->getOperand(1 + X86::AddrDisp).getImm(); in expandMI()
467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI()
468 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); in expandMI()
471 BuildMI(MBB, MBBI, DL, TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWkm))) in expandMI()
474 BuildMI(MBB, MBBI, DL, TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWkm))) in expandMI()
477 for (int i = 0; i < X86::AddrNumOperands; ++i) { in expandMI()
479 if (i == X86::AddrDisp) in expandMI()
498 case X86::MASKPAIR16STORE: { in expandMI()
499 int64_t Disp = MBBI->getOperand(X86::AddrDisp).getImm(); in expandMI()
501 Register Reg = MBBI->getOperand(X86::AddrNumOperands).getReg(); in expandMI()
502 bool SrcIsKill = MBBI->getOperand(X86::AddrNumOperands).isKill(); in expandMI()
503 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI()
504 Register Reg1 = TRI->getSubReg(Reg, X86::sub_mask_1); in expandMI()
507 BuildMI(MBB, MBBI, DL, TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWmk))); in expandMI()
509 BuildMI(MBB, MBBI, DL, TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWmk))); in expandMI()
511 for (int i = 0; i < X86::AddrNumOperands; ++i) { in expandMI()
513 if (i == X86::AddrDisp) in expandMI()
534 case X86::MWAITX_SAVE_RBX: { in expandMI()
544 TII->copyPhysReg(MBB, MBBI, DL, X86::EBX, InArg.getReg(), InArg.isKill()); in expandMI()
546 BuildMI(MBB, MBBI, DL, TII->get(X86::MWAITXrrr)); in expandMI()
549 TII->copyPhysReg(MBB, MBBI, DL, X86::RBX, SaveRbx, /*SrcIsKill*/ true); in expandMI()
557 case X86::PLDTILECFGV: { in expandMI()
558 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::LDTILECFG))); in expandMI()
561 case X86::PTILELOADDV: in expandMI()
562 case X86::PTILELOADDT1V: { in expandMI()
565 unsigned Opc = Opcode == X86::PTILELOADDV in expandMI()
566 ? GET_EGPR_IF_ENABLED(X86::TILELOADD) in expandMI()
567 : GET_EGPR_IF_ENABLED(X86::TILELOADDT1); in expandMI()
571 case X86::PTCMMIMFP16PSV: in expandMI()
572 case X86::PTCMMRLFP16PSV: in expandMI()
573 case X86::PTDPBSSDV: in expandMI()
574 case X86::PTDPBSUDV: in expandMI()
575 case X86::PTDPBUSDV: in expandMI()
576 case X86::PTDPBUUDV: in expandMI()
577 case X86::PTDPBF16PSV: in expandMI()
578 case X86::PTDPFP16PSV: { in expandMI()
584 case X86::PTCMMIMFP16PSV: Opc = X86::TCMMIMFP16PS; break; in expandMI()
585 case X86::PTCMMRLFP16PSV: Opc = X86::TCMMRLFP16PS; break; in expandMI()
586 case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break; in expandMI()
587 case X86::PTDPBSUDV: Opc = X86::TDPBSUD; break; in expandMI()
588 case X86::PTDPBUSDV: Opc = X86::TDPBUSD; break; in expandMI()
589 case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break; in expandMI()
590 case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break; in expandMI()
591 case X86::PTDPFP16PSV: Opc = X86::TDPFP16PS; break; in expandMI()
598 case X86::PTILESTOREDV: { in expandMI()
601 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::TILESTORED))); in expandMI()
605 case X86::PTILEZEROV: { in expandMI()
608 MI.setDesc(TII->get(X86::TILEZERO)); in expandMI()
611 case X86::CALL64pcrel32_RVMARKER: in expandMI()
612 case X86::CALL64r_RVMARKER: in expandMI()
613 case X86::CALL64m_RVMARKER: in expandMI()
616 case X86::ADD32mi_ND: in expandMI()
617 case X86::ADD64mi32_ND: in expandMI()
618 case X86::SUB32mi_ND: in expandMI()
619 case X86::SUB64mi32_ND: in expandMI()
620 case X86::AND32mi_ND: in expandMI()
621 case X86::AND64mi32_ND: in expandMI()
622 case X86::OR32mi_ND: in expandMI()
623 case X86::OR64mi32_ND: in expandMI()
624 case X86::XOR32mi_ND: in expandMI()
625 case X86::XOR64mi32_ND: in expandMI()
626 case X86::ADC32mi_ND: in expandMI()
627 case X86::ADC64mi32_ND: in expandMI()
628 case X86::SBB32mi_ND: in expandMI()
629 case X86::SBB64mi32_ND: { in expandMI()
651 int MemOpNo = X86::getFirstAddrOperandIdx(MI); in expandMI()
652 const MachineOperand &DispOp = MI.getOperand(MemOpNo + X86::AddrDisp); in expandMI()
653 Register Base = MI.getOperand(MemOpNo + X86::AddrBaseReg).getReg(); in expandMI()
658 Register Index = MI.getOperand(MemOpNo + X86::AddrIndexReg).getReg(); in expandMI()
659 unsigned Count = !!MI.getOperand(MemOpNo + X86::AddrSegmentReg).getReg(); in expandMI()
662 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(Base) || in expandMI()
663 X86MCRegisterClasses[X86::GR32RegClassID].contains(Index)) in expandMI()
670 case X86::OP##32mi_ND: \ in expandMI()
671 Opc = X86::OP##32ri; \ in expandMI()
672 LoadOpc = X86::MOV32rm; \ in expandMI()
674 case X86::OP##64mi32_ND: \ in expandMI()
675 Opc = X86::OP##64ri32; \ in expandMI()
676 LoadOpc = X86::MOV64rm; \ in expandMI()
722 assert(VAStartPseudoInstr->getOpcode() == X86::VASTART_SAVE_XMM_REGS); in expandVastartSaveXmmRegs()
761 unsigned MOVOpc = STI->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; in expandVastartSaveXmmRegs()
768 for (int i = 0; i < X86::AddrNumOperands; ++i) { in expandVastartSaveXmmRegs()
769 if (i == X86::AddrDisp) in expandVastartSaveXmmRegs()
785 BuildMI(EntryBlk, DL, TII->get(X86::TEST8rr)) in expandVastartSaveXmmRegs()
788 BuildMI(EntryBlk, DL, TII->get(X86::JCC_1)) in expandVastartSaveXmmRegs()
790 .addImm(X86::COND_E); in expandVastartSaveXmmRegs()
820 // X86::VASTART_SAVE_XMM_REGS which is located in Entry block. in expandPseudosWhichAffectControlFlow()
823 if (Instr.getOpcode() == X86::VASTART_SAVE_XMM_REGS) { in expandPseudosWhichAffectControlFlow()