Lines Matching full:x86
1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // on X86.
45 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
69 FramePtr = Use64BitReg ? X86::RBP : X86::EBP; in X86RegisterInfo()
70 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
73 StackPtr = X86::ESP; in X86RegisterInfo()
74 FramePtr = X86::EBP; in X86RegisterInfo()
75 BasePtr = X86::ESI; in X86RegisterInfo()
89 if (!Is64Bit && Idx == X86::sub_8bit) in getSubClassWithSubReg()
90 Idx = X86::sub_8bit_hi; in getSubClassWithSubReg()
101 if (!Is64Bit && SubIdx == X86::sub_8bit) { in getMatchingSuperRegClass()
102 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); in getMatchingSuperRegClass()
120 if (RC == &X86::GR8_NOREXRegClass) in getLargestLegalSuperClass()
129 case X86::FR32RegClassID: in getLargestLegalSuperClass()
130 case X86::FR64RegClassID: in getLargestLegalSuperClass()
136 case X86::VR128RegClassID: in getLargestLegalSuperClass()
137 case X86::VR256RegClassID: in getLargestLegalSuperClass()
143 case X86::VR128XRegClassID: in getLargestLegalSuperClass()
144 case X86::VR256XRegClassID: in getLargestLegalSuperClass()
150 case X86::FR32XRegClassID: in getLargestLegalSuperClass()
151 case X86::FR64XRegClassID: in getLargestLegalSuperClass()
157 case X86::GR8RegClassID: in getLargestLegalSuperClass()
158 case X86::GR16RegClassID: in getLargestLegalSuperClass()
159 case X86::GR32RegClassID: in getLargestLegalSuperClass()
160 case X86::GR64RegClassID: in getLargestLegalSuperClass()
161 case X86::GR8_NOREX2RegClassID: in getLargestLegalSuperClass()
162 case X86::GR16_NOREX2RegClassID: in getLargestLegalSuperClass()
163 case X86::GR32_NOREX2RegClassID: in getLargestLegalSuperClass()
164 case X86::GR64_NOREX2RegClassID: in getLargestLegalSuperClass()
165 case X86::RFP32RegClassID: in getLargestLegalSuperClass()
166 case X86::RFP64RegClassID: in getLargestLegalSuperClass()
167 case X86::RFP80RegClassID: in getLargestLegalSuperClass()
168 case X86::VR512_0_15RegClassID: in getLargestLegalSuperClass()
169 case X86::VR512RegClassID: in getLargestLegalSuperClass()
188 return &X86::GR64RegClass; in getPointerRegClass()
198 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass in getPointerRegClass()
199 : &X86::LOW32_ADDR_ACCESSRegClass; in getPointerRegClass()
201 return &X86::GR32RegClass; in getPointerRegClass()
204 return &X86::GR64_NOSPRegClass; in getPointerRegClass()
206 return &X86::GR32_NOSPRegClass; in getPointerRegClass()
209 return &X86::GR64_NOREXRegClass; in getPointerRegClass()
210 return &X86::GR32_NOREXRegClass; in getPointerRegClass()
213 return &X86::GR64_NOREX_NOSPRegClass; in getPointerRegClass()
215 return &X86::GR32_NOREX_NOSPRegClass; in getPointerRegClass()
228 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
229 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
240 return &X86::GR64_TCW64RegClass; in getGPRsForTailCall()
242 return &X86::GR64_TCRegClass; in getGPRsForTailCall()
246 return &X86::GR32RegClass; in getGPRsForTailCall()
247 return &X86::GR32_TCRegClass; in getGPRsForTailCall()
252 if (RC == &X86::CCRRegClass) { in getCrossCopyRegClass()
254 return &X86::GR64RegClass; in getCrossCopyRegClass()
256 return &X86::GR32RegClass; in getCrossCopyRegClass()
270 case X86::GR32RegClassID: in getRegPressureLimit()
272 case X86::GR64RegClassID: in getRegPressureLimit()
274 case X86::VR128RegClassID: in getRegPressureLimit()
276 case X86::VR64RegClassID: in getRegPressureLimit()
353 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86"); in getCalleeSavedRegs()
475 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86"); in getCallPreservedMask()
541 Reserved.set(X86::FPCW); in getReservedRegs()
544 Reserved.set(X86::FPSW); in getReservedRegs()
547 Reserved.set(X86::MXCSR); in getReservedRegs()
550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs()
554 Reserved.set(X86::SSP); in getReservedRegs()
557 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs()
562 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs()
581 Reserved.set(X86::CS); in getReservedRegs()
582 Reserved.set(X86::SS); in getReservedRegs()
583 Reserved.set(X86::DS); in getReservedRegs()
584 Reserved.set(X86::ES); in getReservedRegs()
585 Reserved.set(X86::FS); in getReservedRegs()
586 Reserved.set(X86::GS); in getReservedRegs()
590 Reserved.set(X86::ST0 + n); in getReservedRegs()
594 // These 8-bit registers are part of the x86-64 extension even though their in getReservedRegs()
596 Reserved.set(X86::SIL); in getReservedRegs()
597 Reserved.set(X86::DIL); in getReservedRegs()
598 Reserved.set(X86::BPL); in getReservedRegs()
599 Reserved.set(X86::SPL); in getReservedRegs()
600 Reserved.set(X86::SIH); in getReservedRegs()
601 Reserved.set(X86::DIH); in getReservedRegs()
602 Reserved.set(X86::BPH); in getReservedRegs()
603 Reserved.set(X86::SPH); in getReservedRegs()
607 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
611 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
617 for (MCRegAliasIterator AI(X86::XMM16 + n, this, true); AI.isValid(); in getReservedRegs()
625 Reserved.set(X86::R16, X86::R31WH + 1); in getReservedRegs()
628 for (MCRegAliasIterator AI(X86::R14, this, true); AI.isValid(); ++AI) in getReservedRegs()
630 for (MCRegAliasIterator AI(X86::R15, this, true); AI.isValid(); ++AI) in getReservedRegs()
635 {X86::SIL, X86::DIL, X86::BPL, X86::SPL, in getReservedRegs()
636 X86::SIH, X86::DIH, X86::BPH, X86::SPH})); in getReservedRegs()
652 static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) && in getNumSupportedRegs()
653 (X86::K6_K7 + 1 == X86::TMMCFG) && in getNumSupportedRegs()
654 (X86::TMM7 + 1 == X86::R16) && in getNumSupportedRegs()
655 (X86::R31WH + 1 == X86::NUM_TARGET_REGS), in getNumSupportedRegs()
660 return X86::NUM_TARGET_REGS; in getNumSupportedRegs()
662 return X86::TMM7 + 1; in getNumSupportedRegs()
664 return X86::K6_K7 + 1; in getNumSupportedRegs()
666 return X86::YMM15 + 1; in getNumSupportedRegs()
667 return X86::R15WH + 1; in getNumSupportedRegs()
680 SmallVector<MCRegister>{X86::EAX, X86::ECX, X86::EDX}, in isArgumentRegister()
682 (ST.hasMMX() && X86::VR64RegClass.contains(Reg)); in isArgumentRegister()
686 if (CC == CallingConv::X86_64_SysV && IsSubReg(X86::RAX, Reg)) in isArgumentRegister()
690 SmallVector<MCRegister>{X86::RDX, X86::RCX, X86::R8, X86::R9}, in isArgumentRegister()
695 llvm::any_of(SmallVector<MCRegister>{X86::RDI, X86::RSI}, in isArgumentRegister()
700 llvm::any_of(SmallVector<MCRegister>{X86::XMM0, X86::XMM1, X86::XMM2, in isArgumentRegister()
701 X86::XMM3, X86::XMM4, X86::XMM5, in isArgumentRegister()
702 X86::XMM6, X86::XMM7}, in isArgumentRegister()
715 if (TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg)) in isFixedRegister()
720 if (TFI.hasFP(MF) && TRI.isSuperOrSubRegisterEq(X86::RBP, PhysReg)) in isFixedRegister()
727 return RC->getID() == X86::TILERegClassID; in isTileRegisterClass()
738 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) && in adjustStackMapLiveOutMask()
742 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
812 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) || in tryOptimizeLEAtoMOV()
814 MI.getOperand(3).getReg() != X86::NoRegister || in tryOptimizeLEAtoMOV()
816 MI.getOperand(5).getReg() != X86::NoRegister) in tryOptimizeLEAtoMOV()
822 if (Opc == X86::LEA64_32r) in tryOptimizeLEAtoMOV()
835 case X86::CATCHRET: in isFuncletReturnInstr()
836 case X86::CLEANUPRET: in isFuncletReturnInstr()
859 // X86 format. It only has a FI and an offset. in eliminateFrameIndex()
928 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr)) in eliminateFrameIndex()
939 // X86 format. It only has a FI and an offset. in eliminateFrameIndex()
979 case X86::RET: in findDeadCallerSavedReg()
980 case X86::RET32: in findDeadCallerSavedReg()
981 case X86::RET64: in findDeadCallerSavedReg()
982 case X86::RETI32: in findDeadCallerSavedReg()
983 case X86::RETI64: in findDeadCallerSavedReg()
984 case X86::TCRETURNdi: in findDeadCallerSavedReg()
985 case X86::TCRETURNri: in findDeadCallerSavedReg()
986 case X86::TCRETURNmi: in findDeadCallerSavedReg()
987 case X86::TCRETURNdi64: in findDeadCallerSavedReg()
988 case X86::TCRETURNri64: in findDeadCallerSavedReg()
989 case X86::TCRETURNmi64: in findDeadCallerSavedReg()
990 case X86::EH_RETURN: in findDeadCallerSavedReg()
991 case X86::EH_RETURN64: { in findDeadCallerSavedReg()
1004 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
1047 case X86::COPY: { in getTileShape()
1054 case X86::PTILELOADDV: in getTileShape()
1055 case X86::PTILELOADDT1V: in getTileShape()
1056 case X86::PTDPBSSDV: in getTileShape()
1057 case X86::PTDPBSUDV: in getTileShape()
1058 case X86::PTDPBUSDV: in getTileShape()
1059 case X86::PTDPBUUDV: in getTileShape()
1060 case X86::PTILEZEROV: in getTileShape()
1061 case X86::PTDPBF16PSV: in getTileShape()
1062 case X86::PTDPFP16PSV: in getTileShape()
1063 case X86::PTCMMIMFP16PSV: in getTileShape()
1064 case X86::PTCMMRLFP16PSV: in getTileShape()
1085 if (ID != X86::TILERegClassID) in getRegAllocationHints()