Lines Matching full:x86
1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && Base.getReg() == 0 && in is16BitMemOperand()
94 return isMemOperand(MI, Op, X86::GR16RegClassID); in is16BitMemOperand()
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand()
100 if (Base.isReg() && Base.getReg() == X86::EIP) { in is32BitMemOperand()
104 if (Index.isReg() && Index.getReg() == X86::EIZ) in is32BitMemOperand()
106 return isMemOperand(MI, Op, X86::GR32RegClassID); in is32BitMemOperand()
111 return isMemOperand(MI, Op, X86::GR64RegClassID); in is64BitMemOperand()
119 bool Is16BitMode = STI.hasFeature(X86::Is16Bit); in needsAddressSizeOverride()
120 bool Is32BitMode = STI.hasFeature(X86::Is32Bit); in needsAddressSizeOverride()
121 bool Is64BitMode = STI.hasFeature(X86::Is64Bit); in needsAddressSizeOverride()
132 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || in needsAddressSizeOverride()
133 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || in needsAddressSizeOverride()
134 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && in needsAddressSizeOverride()
136 return (!Is32BitMode && siReg == X86::ESI) || in needsAddressSizeOverride()
137 (Is32BitMode && siReg == X86::SI); in needsAddressSizeOverride()
141 return (!Is32BitMode && siReg == X86::ESI) || in needsAddressSizeOverride()
142 (Is32BitMode && siReg == X86::SI); in needsAddressSizeOverride()
146 return (!Is32BitMode && siReg == X86::EDI) || in needsAddressSizeOverride()
147 (Is32BitMode && siReg == X86::DI); in needsAddressSizeOverride()
155 if (STI.hasFeature(X86::Is64Bit)) { in needsAddressSizeOverride()
159 if (STI.hasFeature(X86::Is32Bit)) { in needsAddressSizeOverride()
163 assert(STI.hasFeature(X86::Is16Bit)); in needsAddressSizeOverride()
170 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
180 {codeview::RegisterId::AL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
181 {codeview::RegisterId::CL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
182 {codeview::RegisterId::DL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
183 {codeview::RegisterId::BL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
184 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
185 {codeview::RegisterId::CH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
186 {codeview::RegisterId::DH, X86::DH}, in initLLVMToSEHAndCVRegMapping()
187 {codeview::RegisterId::BH, X86::BH}, in initLLVMToSEHAndCVRegMapping()
188 {codeview::RegisterId::AX, X86::AX}, in initLLVMToSEHAndCVRegMapping()
189 {codeview::RegisterId::CX, X86::CX}, in initLLVMToSEHAndCVRegMapping()
190 {codeview::RegisterId::DX, X86::DX}, in initLLVMToSEHAndCVRegMapping()
191 {codeview::RegisterId::BX, X86::BX}, in initLLVMToSEHAndCVRegMapping()
192 {codeview::RegisterId::SP, X86::SP}, in initLLVMToSEHAndCVRegMapping()
193 {codeview::RegisterId::BP, X86::BP}, in initLLVMToSEHAndCVRegMapping()
194 {codeview::RegisterId::SI, X86::SI}, in initLLVMToSEHAndCVRegMapping()
195 {codeview::RegisterId::DI, X86::DI}, in initLLVMToSEHAndCVRegMapping()
196 {codeview::RegisterId::EAX, X86::EAX}, in initLLVMToSEHAndCVRegMapping()
197 {codeview::RegisterId::ECX, X86::ECX}, in initLLVMToSEHAndCVRegMapping()
198 {codeview::RegisterId::EDX, X86::EDX}, in initLLVMToSEHAndCVRegMapping()
199 {codeview::RegisterId::EBX, X86::EBX}, in initLLVMToSEHAndCVRegMapping()
200 {codeview::RegisterId::ESP, X86::ESP}, in initLLVMToSEHAndCVRegMapping()
201 {codeview::RegisterId::EBP, X86::EBP}, in initLLVMToSEHAndCVRegMapping()
202 {codeview::RegisterId::ESI, X86::ESI}, in initLLVMToSEHAndCVRegMapping()
203 {codeview::RegisterId::EDI, X86::EDI}, in initLLVMToSEHAndCVRegMapping()
205 {codeview::RegisterId::EFLAGS, X86::EFLAGS}, in initLLVMToSEHAndCVRegMapping()
207 {codeview::RegisterId::ST0, X86::ST0}, in initLLVMToSEHAndCVRegMapping()
208 {codeview::RegisterId::ST1, X86::ST1}, in initLLVMToSEHAndCVRegMapping()
209 {codeview::RegisterId::ST2, X86::ST2}, in initLLVMToSEHAndCVRegMapping()
210 {codeview::RegisterId::ST3, X86::ST3}, in initLLVMToSEHAndCVRegMapping()
211 {codeview::RegisterId::ST4, X86::ST4}, in initLLVMToSEHAndCVRegMapping()
212 {codeview::RegisterId::ST5, X86::ST5}, in initLLVMToSEHAndCVRegMapping()
213 {codeview::RegisterId::ST6, X86::ST6}, in initLLVMToSEHAndCVRegMapping()
214 {codeview::RegisterId::ST7, X86::ST7}, in initLLVMToSEHAndCVRegMapping()
216 {codeview::RegisterId::ST0, X86::FP0}, in initLLVMToSEHAndCVRegMapping()
217 {codeview::RegisterId::ST1, X86::FP1}, in initLLVMToSEHAndCVRegMapping()
218 {codeview::RegisterId::ST2, X86::FP2}, in initLLVMToSEHAndCVRegMapping()
219 {codeview::RegisterId::ST3, X86::FP3}, in initLLVMToSEHAndCVRegMapping()
220 {codeview::RegisterId::ST4, X86::FP4}, in initLLVMToSEHAndCVRegMapping()
221 {codeview::RegisterId::ST5, X86::FP5}, in initLLVMToSEHAndCVRegMapping()
222 {codeview::RegisterId::ST6, X86::FP6}, in initLLVMToSEHAndCVRegMapping()
223 {codeview::RegisterId::ST7, X86::FP7}, in initLLVMToSEHAndCVRegMapping()
225 {codeview::RegisterId::MM0, X86::MM0}, in initLLVMToSEHAndCVRegMapping()
226 {codeview::RegisterId::MM1, X86::MM1}, in initLLVMToSEHAndCVRegMapping()
227 {codeview::RegisterId::MM2, X86::MM2}, in initLLVMToSEHAndCVRegMapping()
228 {codeview::RegisterId::MM3, X86::MM3}, in initLLVMToSEHAndCVRegMapping()
229 {codeview::RegisterId::MM4, X86::MM4}, in initLLVMToSEHAndCVRegMapping()
230 {codeview::RegisterId::MM5, X86::MM5}, in initLLVMToSEHAndCVRegMapping()
231 {codeview::RegisterId::MM6, X86::MM6}, in initLLVMToSEHAndCVRegMapping()
232 {codeview::RegisterId::MM7, X86::MM7}, in initLLVMToSEHAndCVRegMapping()
234 {codeview::RegisterId::XMM0, X86::XMM0}, in initLLVMToSEHAndCVRegMapping()
235 {codeview::RegisterId::XMM1, X86::XMM1}, in initLLVMToSEHAndCVRegMapping()
236 {codeview::RegisterId::XMM2, X86::XMM2}, in initLLVMToSEHAndCVRegMapping()
237 {codeview::RegisterId::XMM3, X86::XMM3}, in initLLVMToSEHAndCVRegMapping()
238 {codeview::RegisterId::XMM4, X86::XMM4}, in initLLVMToSEHAndCVRegMapping()
239 {codeview::RegisterId::XMM5, X86::XMM5}, in initLLVMToSEHAndCVRegMapping()
240 {codeview::RegisterId::XMM6, X86::XMM6}, in initLLVMToSEHAndCVRegMapping()
241 {codeview::RegisterId::XMM7, X86::XMM7}, in initLLVMToSEHAndCVRegMapping()
243 {codeview::RegisterId::XMM8, X86::XMM8}, in initLLVMToSEHAndCVRegMapping()
244 {codeview::RegisterId::XMM9, X86::XMM9}, in initLLVMToSEHAndCVRegMapping()
245 {codeview::RegisterId::XMM10, X86::XMM10}, in initLLVMToSEHAndCVRegMapping()
246 {codeview::RegisterId::XMM11, X86::XMM11}, in initLLVMToSEHAndCVRegMapping()
247 {codeview::RegisterId::XMM12, X86::XMM12}, in initLLVMToSEHAndCVRegMapping()
248 {codeview::RegisterId::XMM13, X86::XMM13}, in initLLVMToSEHAndCVRegMapping()
249 {codeview::RegisterId::XMM14, X86::XMM14}, in initLLVMToSEHAndCVRegMapping()
250 {codeview::RegisterId::XMM15, X86::XMM15}, in initLLVMToSEHAndCVRegMapping()
252 {codeview::RegisterId::SIL, X86::SIL}, in initLLVMToSEHAndCVRegMapping()
253 {codeview::RegisterId::DIL, X86::DIL}, in initLLVMToSEHAndCVRegMapping()
254 {codeview::RegisterId::BPL, X86::BPL}, in initLLVMToSEHAndCVRegMapping()
255 {codeview::RegisterId::SPL, X86::SPL}, in initLLVMToSEHAndCVRegMapping()
256 {codeview::RegisterId::RAX, X86::RAX}, in initLLVMToSEHAndCVRegMapping()
257 {codeview::RegisterId::RBX, X86::RBX}, in initLLVMToSEHAndCVRegMapping()
258 {codeview::RegisterId::RCX, X86::RCX}, in initLLVMToSEHAndCVRegMapping()
259 {codeview::RegisterId::RDX, X86::RDX}, in initLLVMToSEHAndCVRegMapping()
260 {codeview::RegisterId::RSI, X86::RSI}, in initLLVMToSEHAndCVRegMapping()
261 {codeview::RegisterId::RDI, X86::RDI}, in initLLVMToSEHAndCVRegMapping()
262 {codeview::RegisterId::RBP, X86::RBP}, in initLLVMToSEHAndCVRegMapping()
263 {codeview::RegisterId::RSP, X86::RSP}, in initLLVMToSEHAndCVRegMapping()
264 {codeview::RegisterId::R8, X86::R8}, in initLLVMToSEHAndCVRegMapping()
265 {codeview::RegisterId::R9, X86::R9}, in initLLVMToSEHAndCVRegMapping()
266 {codeview::RegisterId::R10, X86::R10}, in initLLVMToSEHAndCVRegMapping()
267 {codeview::RegisterId::R11, X86::R11}, in initLLVMToSEHAndCVRegMapping()
268 {codeview::RegisterId::R12, X86::R12}, in initLLVMToSEHAndCVRegMapping()
269 {codeview::RegisterId::R13, X86::R13}, in initLLVMToSEHAndCVRegMapping()
270 {codeview::RegisterId::R14, X86::R14}, in initLLVMToSEHAndCVRegMapping()
271 {codeview::RegisterId::R15, X86::R15}, in initLLVMToSEHAndCVRegMapping()
272 {codeview::RegisterId::R8B, X86::R8B}, in initLLVMToSEHAndCVRegMapping()
273 {codeview::RegisterId::R9B, X86::R9B}, in initLLVMToSEHAndCVRegMapping()
274 {codeview::RegisterId::R10B, X86::R10B}, in initLLVMToSEHAndCVRegMapping()
275 {codeview::RegisterId::R11B, X86::R11B}, in initLLVMToSEHAndCVRegMapping()
276 {codeview::RegisterId::R12B, X86::R12B}, in initLLVMToSEHAndCVRegMapping()
277 {codeview::RegisterId::R13B, X86::R13B}, in initLLVMToSEHAndCVRegMapping()
278 {codeview::RegisterId::R14B, X86::R14B}, in initLLVMToSEHAndCVRegMapping()
279 {codeview::RegisterId::R15B, X86::R15B}, in initLLVMToSEHAndCVRegMapping()
280 {codeview::RegisterId::R8W, X86::R8W}, in initLLVMToSEHAndCVRegMapping()
281 {codeview::RegisterId::R9W, X86::R9W}, in initLLVMToSEHAndCVRegMapping()
282 {codeview::RegisterId::R10W, X86::R10W}, in initLLVMToSEHAndCVRegMapping()
283 {codeview::RegisterId::R11W, X86::R11W}, in initLLVMToSEHAndCVRegMapping()
284 {codeview::RegisterId::R12W, X86::R12W}, in initLLVMToSEHAndCVRegMapping()
285 {codeview::RegisterId::R13W, X86::R13W}, in initLLVMToSEHAndCVRegMapping()
286 {codeview::RegisterId::R14W, X86::R14W}, in initLLVMToSEHAndCVRegMapping()
287 {codeview::RegisterId::R15W, X86::R15W}, in initLLVMToSEHAndCVRegMapping()
288 {codeview::RegisterId::R8D, X86::R8D}, in initLLVMToSEHAndCVRegMapping()
289 {codeview::RegisterId::R9D, X86::R9D}, in initLLVMToSEHAndCVRegMapping()
290 {codeview::RegisterId::R10D, X86::R10D}, in initLLVMToSEHAndCVRegMapping()
291 {codeview::RegisterId::R11D, X86::R11D}, in initLLVMToSEHAndCVRegMapping()
292 {codeview::RegisterId::R12D, X86::R12D}, in initLLVMToSEHAndCVRegMapping()
293 {codeview::RegisterId::R13D, X86::R13D}, in initLLVMToSEHAndCVRegMapping()
294 {codeview::RegisterId::R14D, X86::R14D}, in initLLVMToSEHAndCVRegMapping()
295 {codeview::RegisterId::R15D, X86::R15D}, in initLLVMToSEHAndCVRegMapping()
296 {codeview::RegisterId::AMD64_YMM0, X86::YMM0}, in initLLVMToSEHAndCVRegMapping()
297 {codeview::RegisterId::AMD64_YMM1, X86::YMM1}, in initLLVMToSEHAndCVRegMapping()
298 {codeview::RegisterId::AMD64_YMM2, X86::YMM2}, in initLLVMToSEHAndCVRegMapping()
299 {codeview::RegisterId::AMD64_YMM3, X86::YMM3}, in initLLVMToSEHAndCVRegMapping()
300 {codeview::RegisterId::AMD64_YMM4, X86::YMM4}, in initLLVMToSEHAndCVRegMapping()
301 {codeview::RegisterId::AMD64_YMM5, X86::YMM5}, in initLLVMToSEHAndCVRegMapping()
302 {codeview::RegisterId::AMD64_YMM6, X86::YMM6}, in initLLVMToSEHAndCVRegMapping()
303 {codeview::RegisterId::AMD64_YMM7, X86::YMM7}, in initLLVMToSEHAndCVRegMapping()
304 {codeview::RegisterId::AMD64_YMM8, X86::YMM8}, in initLLVMToSEHAndCVRegMapping()
305 {codeview::RegisterId::AMD64_YMM9, X86::YMM9}, in initLLVMToSEHAndCVRegMapping()
306 {codeview::RegisterId::AMD64_YMM10, X86::YMM10}, in initLLVMToSEHAndCVRegMapping()
307 {codeview::RegisterId::AMD64_YMM11, X86::YMM11}, in initLLVMToSEHAndCVRegMapping()
308 {codeview::RegisterId::AMD64_YMM12, X86::YMM12}, in initLLVMToSEHAndCVRegMapping()
309 {codeview::RegisterId::AMD64_YMM13, X86::YMM13}, in initLLVMToSEHAndCVRegMapping()
310 {codeview::RegisterId::AMD64_YMM14, X86::YMM14}, in initLLVMToSEHAndCVRegMapping()
311 {codeview::RegisterId::AMD64_YMM15, X86::YMM15}, in initLLVMToSEHAndCVRegMapping()
312 {codeview::RegisterId::AMD64_YMM16, X86::YMM16}, in initLLVMToSEHAndCVRegMapping()
313 {codeview::RegisterId::AMD64_YMM17, X86::YMM17}, in initLLVMToSEHAndCVRegMapping()
314 {codeview::RegisterId::AMD64_YMM18, X86::YMM18}, in initLLVMToSEHAndCVRegMapping()
315 {codeview::RegisterId::AMD64_YMM19, X86::YMM19}, in initLLVMToSEHAndCVRegMapping()
316 {codeview::RegisterId::AMD64_YMM20, X86::YMM20}, in initLLVMToSEHAndCVRegMapping()
317 {codeview::RegisterId::AMD64_YMM21, X86::YMM21}, in initLLVMToSEHAndCVRegMapping()
318 {codeview::RegisterId::AMD64_YMM22, X86::YMM22}, in initLLVMToSEHAndCVRegMapping()
319 {codeview::RegisterId::AMD64_YMM23, X86::YMM23}, in initLLVMToSEHAndCVRegMapping()
320 {codeview::RegisterId::AMD64_YMM24, X86::YMM24}, in initLLVMToSEHAndCVRegMapping()
321 {codeview::RegisterId::AMD64_YMM25, X86::YMM25}, in initLLVMToSEHAndCVRegMapping()
322 {codeview::RegisterId::AMD64_YMM26, X86::YMM26}, in initLLVMToSEHAndCVRegMapping()
323 {codeview::RegisterId::AMD64_YMM27, X86::YMM27}, in initLLVMToSEHAndCVRegMapping()
324 {codeview::RegisterId::AMD64_YMM28, X86::YMM28}, in initLLVMToSEHAndCVRegMapping()
325 {codeview::RegisterId::AMD64_YMM29, X86::YMM29}, in initLLVMToSEHAndCVRegMapping()
326 {codeview::RegisterId::AMD64_YMM30, X86::YMM30}, in initLLVMToSEHAndCVRegMapping()
327 {codeview::RegisterId::AMD64_YMM31, X86::YMM31}, in initLLVMToSEHAndCVRegMapping()
328 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0}, in initLLVMToSEHAndCVRegMapping()
329 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1}, in initLLVMToSEHAndCVRegMapping()
330 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2}, in initLLVMToSEHAndCVRegMapping()
331 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3}, in initLLVMToSEHAndCVRegMapping()
332 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4}, in initLLVMToSEHAndCVRegMapping()
333 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5}, in initLLVMToSEHAndCVRegMapping()
334 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6}, in initLLVMToSEHAndCVRegMapping()
335 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7}, in initLLVMToSEHAndCVRegMapping()
336 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8}, in initLLVMToSEHAndCVRegMapping()
337 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9}, in initLLVMToSEHAndCVRegMapping()
338 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10}, in initLLVMToSEHAndCVRegMapping()
339 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11}, in initLLVMToSEHAndCVRegMapping()
340 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12}, in initLLVMToSEHAndCVRegMapping()
341 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13}, in initLLVMToSEHAndCVRegMapping()
342 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14}, in initLLVMToSEHAndCVRegMapping()
343 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15}, in initLLVMToSEHAndCVRegMapping()
344 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16}, in initLLVMToSEHAndCVRegMapping()
345 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17}, in initLLVMToSEHAndCVRegMapping()
346 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18}, in initLLVMToSEHAndCVRegMapping()
347 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19}, in initLLVMToSEHAndCVRegMapping()
348 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20}, in initLLVMToSEHAndCVRegMapping()
349 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21}, in initLLVMToSEHAndCVRegMapping()
350 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22}, in initLLVMToSEHAndCVRegMapping()
351 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23}, in initLLVMToSEHAndCVRegMapping()
352 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24}, in initLLVMToSEHAndCVRegMapping()
353 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25}, in initLLVMToSEHAndCVRegMapping()
354 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26}, in initLLVMToSEHAndCVRegMapping()
355 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27}, in initLLVMToSEHAndCVRegMapping()
356 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28}, in initLLVMToSEHAndCVRegMapping()
357 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29}, in initLLVMToSEHAndCVRegMapping()
358 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30}, in initLLVMToSEHAndCVRegMapping()
359 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31}, in initLLVMToSEHAndCVRegMapping()
360 {codeview::RegisterId::AMD64_K0, X86::K0}, in initLLVMToSEHAndCVRegMapping()
361 {codeview::RegisterId::AMD64_K1, X86::K1}, in initLLVMToSEHAndCVRegMapping()
362 {codeview::RegisterId::AMD64_K2, X86::K2}, in initLLVMToSEHAndCVRegMapping()
363 {codeview::RegisterId::AMD64_K3, X86::K3}, in initLLVMToSEHAndCVRegMapping()
364 {codeview::RegisterId::AMD64_K4, X86::K4}, in initLLVMToSEHAndCVRegMapping()
365 {codeview::RegisterId::AMD64_K5, X86::K5}, in initLLVMToSEHAndCVRegMapping()
366 {codeview::RegisterId::AMD64_K6, X86::K6}, in initLLVMToSEHAndCVRegMapping()
367 {codeview::RegisterId::AMD64_K7, X86::K7}, in initLLVMToSEHAndCVRegMapping()
368 {codeview::RegisterId::AMD64_XMM16, X86::XMM16}, in initLLVMToSEHAndCVRegMapping()
369 {codeview::RegisterId::AMD64_XMM17, X86::XMM17}, in initLLVMToSEHAndCVRegMapping()
370 {codeview::RegisterId::AMD64_XMM18, X86::XMM18}, in initLLVMToSEHAndCVRegMapping()
371 {codeview::RegisterId::AMD64_XMM19, X86::XMM19}, in initLLVMToSEHAndCVRegMapping()
372 {codeview::RegisterId::AMD64_XMM20, X86::XMM20}, in initLLVMToSEHAndCVRegMapping()
373 {codeview::RegisterId::AMD64_XMM21, X86::XMM21}, in initLLVMToSEHAndCVRegMapping()
374 {codeview::RegisterId::AMD64_XMM22, X86::XMM22}, in initLLVMToSEHAndCVRegMapping()
375 {codeview::RegisterId::AMD64_XMM23, X86::XMM23}, in initLLVMToSEHAndCVRegMapping()
376 {codeview::RegisterId::AMD64_XMM24, X86::XMM24}, in initLLVMToSEHAndCVRegMapping()
377 {codeview::RegisterId::AMD64_XMM25, X86::XMM25}, in initLLVMToSEHAndCVRegMapping()
378 {codeview::RegisterId::AMD64_XMM26, X86::XMM26}, in initLLVMToSEHAndCVRegMapping()
379 {codeview::RegisterId::AMD64_XMM27, X86::XMM27}, in initLLVMToSEHAndCVRegMapping()
380 {codeview::RegisterId::AMD64_XMM28, X86::XMM28}, in initLLVMToSEHAndCVRegMapping()
381 {codeview::RegisterId::AMD64_XMM29, X86::XMM29}, in initLLVMToSEHAndCVRegMapping()
382 {codeview::RegisterId::AMD64_XMM30, X86::XMM30}, in initLLVMToSEHAndCVRegMapping()
383 {codeview::RegisterId::AMD64_XMM31, X86::XMM31}, in initLLVMToSEHAndCVRegMapping()
393 assert(!ArchFS.empty() && "Failed to parse X86 triple"); in createX86MCSubtargetInfo()
423 ? X86::RIP // Should have dwarf #16. in createX86MCRegisterInfo()
424 : X86::EIP; // Should have dwarf #8. in createX86MCRegisterInfo()
468 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
474 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; in createX86MCAsmInfo()
546 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); in clearsSuperRegisters()
547 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); in clearsSuperRegisters()
548 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); in clearsSuperRegisters()
551 // On X86-64, a general purpose integer register is viewed as a 64-bit in clearsSuperRegisters()
636 case Triple::x86: in findPltEntries()
664 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); in evaluateMemoryOperandAddress()
665 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress()
666 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress()
667 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); in evaluateMemoryOperandAddress()
668 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); in evaluateMemoryOperandAddress()
674 if (BaseReg.getReg() == X86::RIP) in evaluateMemoryOperandAddress()
683 if (Inst.getOpcode() != X86::LEA64r) in getMemoryOperandRelocationOffset()
690 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); in getMemoryOperandRelocationOffset()
691 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset()
692 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset()
693 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); in getMemoryOperandRelocationOffset()
694 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); in getMemoryOperandRelocationOffset()
696 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() != 0 || in getMemoryOperandRelocationOffset()
765 return X86::NoRegister; in getX86SubSuperRegister()
767 case X86::R1: \ in getX86SubSuperRegister()
768 case X86::R2: \ in getX86SubSuperRegister()
769 case X86::R3: \ in getX86SubSuperRegister()
770 case X86::R4: \ in getX86SubSuperRegister()
771 return X86::R; in getX86SubSuperRegister()
773 case X86::AH: \ in getX86SubSuperRegister()
776 case X86::DH: \ in getX86SubSuperRegister()
779 case X86::CH: \ in getX86SubSuperRegister()
782 case X86::BH: \ in getX86SubSuperRegister()