Lines Matching full:x86
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
335 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32; in getRetOpcode()
374 case X86::TAILJMPr: in convertTailJumpOpcode()
375 Opcode = X86::JMP32r; in convertTailJumpOpcode()
377 case X86::TAILJMPm: in convertTailJumpOpcode()
378 Opcode = X86::JMP32m; in convertTailJumpOpcode()
380 case X86::TAILJMPr64: in convertTailJumpOpcode()
381 Opcode = X86::JMP64r; in convertTailJumpOpcode()
383 case X86::TAILJMPm64: in convertTailJumpOpcode()
384 Opcode = X86::JMP64m; in convertTailJumpOpcode()
386 case X86::TAILJMPr64_REX: in convertTailJumpOpcode()
387 Opcode = X86::JMP64r_REX; in convertTailJumpOpcode()
389 case X86::TAILJMPm64_REX: in convertTailJumpOpcode()
390 Opcode = X86::JMP64m_REX; in convertTailJumpOpcode()
392 case X86::TAILJMPd: in convertTailJumpOpcode()
393 case X86::TAILJMPd64: in convertTailJumpOpcode()
394 Opcode = X86::JMP_1; in convertTailJumpOpcode()
396 case X86::TAILJMPd_CC: in convertTailJumpOpcode()
397 case X86::TAILJMPd64_CC: in convertTailJumpOpcode()
398 Opcode = X86::JCC_1; in convertTailJumpOpcode()
413 if (X86::optimizeInstFromVEX3ToVEX2(OutMI, MI->getDesc()) || in Lower()
414 X86::optimizeShiftRotateWithImmediateOne(OutMI) || in Lower()
415 X86::optimizeVPCMPWithImmediateOneOrSix(OutMI) || in Lower()
416 X86::optimizeMOVSX(OutMI) || X86::optimizeINCDEC(OutMI, In64BitMode) || in Lower()
417 X86::optimizeMOV(OutMI, In64BitMode) || in Lower()
418 X86::optimizeToFixedRegisterOrShortImmediateForm(OutMI)) in Lower()
423 case X86::LEA64_32r: in Lower()
424 case X86::LEA64r: in Lower()
425 case X86::LEA16r: in Lower()
426 case X86::LEA32r: in Lower()
428 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands && in Lower()
430 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && in Lower()
433 case X86::MULX32Hrr: in Lower()
434 case X86::MULX32Hrm: in Lower()
435 case X86::MULX64Hrr: in Lower()
436 case X86::MULX64Hrm: { in Lower()
441 case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break; in Lower()
442 case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break; in Lower()
443 case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break; in Lower()
444 case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break; in Lower()
456 case X86::CALL64r: in Lower()
457 case X86::CALL64pcrel32: in Lower()
460 case X86::EH_RETURN: in Lower()
461 case X86::EH_RETURN64: { in Lower()
466 case X86::CLEANUPRET: { in Lower()
472 case X86::CATCHRET: { in Lower()
475 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX; in Lower()
483 case X86::TAILJMPr: in Lower()
484 case X86::TAILJMPr64: in Lower()
485 case X86::TAILJMPr64_REX: in Lower()
486 case X86::TAILJMPd: in Lower()
487 case X86::TAILJMPd64: in Lower()
491 case X86::TAILJMPd_CC: in Lower()
492 case X86::TAILJMPd64_CC: in Lower()
496 case X86::TAILJMPm: in Lower()
497 case X86::TAILJMPm64: in Lower()
498 case X86::TAILJMPm64_REX: in Lower()
499 assert(OutMI.getNumOperands() == X86::AddrNumOperands && in Lower()
503 case X86::MASKMOVDQU: in Lower()
504 case X86::VMASKMOVDQU: in Lower()
506 OutMI.setFlags(X86::IP_HAS_AD_SIZE); in Lower()
508 case X86::BSF16rm: in Lower()
509 case X86::BSF16rr: in Lower()
510 case X86::BSF32rm: in Lower()
511 case X86::BSF32rr: in Lower()
512 case X86::BSF64rm: in Lower()
513 case X86::BSF64rr: { in Lower()
519 MI->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in Lower()
521 OutMI.setFlags(X86::IP_HAS_REPEAT); in Lower()
538 case X86::TLS_addr32: in LowerTlsAddr()
539 case X86::TLS_addr64: in LowerTlsAddr()
540 case X86::TLS_addrX32: in LowerTlsAddr()
543 case X86::TLS_base_addr32: in LowerTlsAddr()
546 case X86::TLS_base_addr64: in LowerTlsAddr()
547 case X86::TLS_base_addrX32: in LowerTlsAddr()
550 case X86::TLS_desc32: in LowerTlsAddr()
551 case X86::TLS_desc64: in LowerTlsAddr()
574 MCInstBuilder(Is64BitsLP64 ? X86::LEA64r : X86::LEA32r) in LowerTlsAddr()
575 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX) in LowerTlsAddr()
576 .addReg(Is64Bits ? X86::RIP : X86::EBX) in LowerTlsAddr()
582 MCInstBuilder(Is64Bits ? X86::CALL64m : X86::CALL32m) in LowerTlsAddr()
583 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX) in LowerTlsAddr()
591 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); in LowerTlsAddr()
592 EmitAndCountInstruction(MCInstBuilder(X86::LEA64r) in LowerTlsAddr()
593 .addReg(X86::RDI) in LowerTlsAddr()
594 .addReg(X86::RIP) in LowerTlsAddr()
602 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); in LowerTlsAddr()
603 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); in LowerTlsAddr()
604 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX)); in LowerTlsAddr()
609 EmitAndCountInstruction(MCInstBuilder(X86::CALL64m) in LowerTlsAddr()
610 .addReg(X86::RIP) in LowerTlsAddr()
617 MCInstBuilder(X86::CALL64pcrel32) in LowerTlsAddr()
623 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r) in LowerTlsAddr()
624 .addReg(X86::EAX) in LowerTlsAddr()
627 .addReg(X86::EBX) in LowerTlsAddr()
631 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r) in LowerTlsAddr()
632 .addReg(X86::EAX) in LowerTlsAddr()
633 .addReg(X86::EBX) in LowerTlsAddr()
644 EmitAndCountInstruction(MCInstBuilder(X86::CALL32m) in LowerTlsAddr()
645 .addReg(X86::EBX) in LowerTlsAddr()
652 MCInstBuilder(X86::CALLpcrel32) in LowerTlsAddr()
670 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP)) in emitNop()
672 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP)) in emitNop()
674 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP)) in emitNop()
687 BaseReg = X86::RAX; in emitNop()
695 Opc = X86::NOOP; in emitNop()
699 Opc = X86::XCHG16ar; in emitNop()
703 Opc = X86::NOOPL; in emitNop()
707 Opc = X86::NOOPL; in emitNop()
712 Opc = X86::NOOPL; in emitNop()
714 IndexReg = X86::RAX; in emitNop()
718 Opc = X86::NOOPW; in emitNop()
720 IndexReg = X86::RAX; in emitNop()
724 Opc = X86::NOOPL; in emitNop()
729 Opc = X86::NOOPL; in emitNop()
731 IndexReg = X86::RAX; in emitNop()
735 Opc = X86::NOOPW; in emitNop()
737 IndexReg = X86::RAX; in emitNop()
741 Opc = X86::NOOPW; in emitNop()
743 IndexReg = X86::RAX; in emitNop()
744 SegmentReg = X86::CS; in emitNop()
755 case X86::NOOP: in emitNop()
758 case X86::XCHG16ar: in emitNop()
759 OS.emitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), in emitNop()
762 case X86::NOOPL: in emitNop()
763 case X86::NOOPW: in emitNop()
777 /// Emit the optimal amount of multi-byte nops on X86.
790 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); in LowerSTATEPOINT()
807 CallOpcode = X86::CALL64pcrel32; in LowerSTATEPOINT()
815 CallOpcode = X86::CALL64pcrel32; in LowerSTATEPOINT()
827 CallOpcode = X86::CALL64r; in LowerSTATEPOINT()
873 if (DefRegister != X86::NoRegister) in LowerFAULTING_OP()
894 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32) in LowerFENTRY_CALL()
903 // returns a 1-byte X86::NOOP, which means the offset is the same in in LowerKCFI_CHECK()
922 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D; in LowerKCFI_CHECK()
924 MCInstBuilder(X86::MOV32ri).addReg(TempReg).addImm(-MaskKCFIType(Type))); in LowerKCFI_CHECK()
925 EmitAndCountInstruction(MCInstBuilder(X86::ADD32rm) in LowerKCFI_CHECK()
926 .addReg(X86::NoRegister) in LowerKCFI_CHECK()
930 .addReg(X86::NoRegister) in LowerKCFI_CHECK()
932 .addReg(X86::NoRegister)); in LowerKCFI_CHECK()
936 MCInstBuilder(X86::JCC_1) in LowerKCFI_CHECK()
938 .addImm(X86::COND_E)); in LowerKCFI_CHECK()
942 EmitAndCountInstruction(MCInstBuilder(X86::TRAP)); in LowerKCFI_CHECK()
975 MCInstBuilder(X86::CALL64pcrel32) in LowerASAN_CHECK_MEMACCESS()
1013 MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI), in LowerPATCHABLE_OP()
1041 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); in LowerPATCHPOINT()
1085 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); in LowerPATCHPOINT()
1090 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); in LowerPATCHPOINT()
1103 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64"); in LowerPATCHABLE_EVENT_CALL()
1107 // We want to emit the following pattern, which follows the x86 calling in LowerPATCHABLE_EVENT_CALL()
1139 const Register DestRegs[] = {X86::RDI, X86::RSI}; in LowerPATCHABLE_EVENT_CALL()
1158 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1171 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1181 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32) in LowerPATCHABLE_EVENT_CALL()
1187 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1201 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64"); in LowerPATCHABLE_TYPED_EVENT_CALL()
1205 // We want to emit the following pattern, which follows the x86 calling in LowerPATCHABLE_TYPED_EVENT_CALL()
1235 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8, in LowerPATCHABLE_TYPED_EVENT_CALL()
1238 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX}; in LowerPATCHABLE_TYPED_EVENT_CALL()
1258 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); in LowerPATCHABLE_TYPED_EVENT_CALL()
1276 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_TYPED_EVENT_CALL()
1286 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32) in LowerPATCHABLE_TYPED_EVENT_CALL()
1292 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); in LowerPATCHABLE_TYPED_EVENT_CALL()
1350 // PATCHABLE_RET X86::RET ... in LowerPATCHABLE_RET()
1380 bool IsConditional = TC.getOpcode() == X86::JCC_1; in LowerPATCHABLE_TAIL_CALL()
1396 MCInstBuilder(X86::JCC_1) in LowerPATCHABLE_TAIL_CALL()
1398 .addImm(X86::GetOppositeBranchCondition( in LowerPATCHABLE_TAIL_CALL()
1399 static_cast<X86::CondCode>(MI.getOperand(2).getImm())))); in LowerPATCHABLE_TAIL_CALL()
1400 TC.setOpcode(X86::JMP_1); in LowerPATCHABLE_TAIL_CALL()
1621 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) { in printZeroUpperMove()
1641 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) { in printBroadcast()
1659 auto *C = X86::getConstantFromPool(*MI, SrcIdx); in printExtend()
1701 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in printZeroExtend()
1715 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86. in EmitSEHInstruction()
1720 case X86::SEH_PushReg: in EmitSEHInstruction()
1723 case X86::SEH_StackAlloc: in EmitSEHInstruction()
1726 case X86::SEH_StackAlign: in EmitSEHInstruction()
1729 case X86::SEH_SetFrame: in EmitSEHInstruction()
1734 case X86::SEH_EndPrologue: in EmitSEHInstruction()
1737 case X86::SEH_SaveReg: in EmitSEHInstruction()
1738 case X86::SEH_SaveXMM: in EmitSEHInstruction()
1739 case X86::SEH_PushFrame: in EmitSEHInstruction()
1750 case X86::SEH_PushReg: in EmitSEHInstruction()
1754 case X86::SEH_SaveReg: in EmitSEHInstruction()
1759 case X86::SEH_SaveXMM: in EmitSEHInstruction()
1764 case X86::SEH_StackAlloc: in EmitSEHInstruction()
1768 case X86::SEH_SetFrame: in EmitSEHInstruction()
1773 case X86::SEH_PushFrame: in EmitSEHInstruction()
1777 case X86::SEH_EndPrologue: in EmitSEHInstruction()
1792 case X86::PSHUFBrm: in addConstantComments()
1793 case X86::VPSHUFBrm: in addConstantComments()
1794 case X86::VPSHUFBYrm: in addConstantComments()
1795 case X86::VPSHUFBZ128rm: in addConstantComments()
1796 case X86::VPSHUFBZ128rmk: in addConstantComments()
1797 case X86::VPSHUFBZ128rmkz: in addConstantComments()
1798 case X86::VPSHUFBZ256rm: in addConstantComments()
1799 case X86::VPSHUFBZ256rmk: in addConstantComments()
1800 case X86::VPSHUFBZ256rmkz: in addConstantComments()
1801 case X86::VPSHUFBZrm: in addConstantComments()
1802 case X86::VPSHUFBZrmk: in addConstantComments()
1803 case X86::VPSHUFBZrmkz: { in addConstantComments()
1805 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1806 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1815 case X86::VPERMILPSrm: in addConstantComments()
1816 case X86::VPERMILPSYrm: in addConstantComments()
1817 case X86::VPERMILPSZ128rm: in addConstantComments()
1818 case X86::VPERMILPSZ128rmk: in addConstantComments()
1819 case X86::VPERMILPSZ128rmkz: in addConstantComments()
1820 case X86::VPERMILPSZ256rm: in addConstantComments()
1821 case X86::VPERMILPSZ256rmk: in addConstantComments()
1822 case X86::VPERMILPSZ256rmkz: in addConstantComments()
1823 case X86::VPERMILPSZrm: in addConstantComments()
1824 case X86::VPERMILPSZrmk: in addConstantComments()
1825 case X86::VPERMILPSZrmkz: { in addConstantComments()
1827 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1828 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1836 case X86::VPERMILPDrm: in addConstantComments()
1837 case X86::VPERMILPDYrm: in addConstantComments()
1838 case X86::VPERMILPDZ128rm: in addConstantComments()
1839 case X86::VPERMILPDZ128rmk: in addConstantComments()
1840 case X86::VPERMILPDZ128rmkz: in addConstantComments()
1841 case X86::VPERMILPDZ256rm: in addConstantComments()
1842 case X86::VPERMILPDZ256rmk: in addConstantComments()
1843 case X86::VPERMILPDZ256rmkz: in addConstantComments()
1844 case X86::VPERMILPDZrm: in addConstantComments()
1845 case X86::VPERMILPDZrmk: in addConstantComments()
1846 case X86::VPERMILPDZrmkz: { in addConstantComments()
1848 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1849 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1858 case X86::VPERMIL2PDrm: in addConstantComments()
1859 case X86::VPERMIL2PSrm: in addConstantComments()
1860 case X86::VPERMIL2PDYrm: in addConstantComments()
1861 case X86::VPERMIL2PSYrm: { in addConstantComments()
1862 assert(MI->getNumOperands() >= (3 + X86::AddrNumOperands + 1) && in addConstantComments()
1872 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break; in addConstantComments()
1873 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break; in addConstantComments()
1876 if (auto *C = X86::getConstantFromPool(*MI, 3)) { in addConstantComments()
1877 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1886 case X86::VPPERMrrm: { in addConstantComments()
1887 if (auto *C = X86::getConstantFromPool(*MI, 3)) { in addConstantComments()
1888 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1897 case X86::MMX_MOVQ64rm: { in addConstantComments()
1898 if (auto *C = X86::getConstantFromPool(*MI, 1)) { in addConstantComments()
1912 case X86::Prefix##Instr##Suffix##rm##Postfix: in addConstantComments()
1931 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1936 X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1952 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1957 X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1972 case X86::MOVSDrm: in addConstantComments()
1973 case X86::VMOVSDrm: in addConstantComments()
1974 MASK_AVX512_CASE(X86::VMOVSDZrm) in addConstantComments()
1975 case X86::MOVSDrm_alt: in addConstantComments()
1976 case X86::VMOVSDrm_alt: in addConstantComments()
1977 case X86::VMOVSDZrm_alt: in addConstantComments()
1978 case X86::MOVQI2PQIrm: in addConstantComments()
1979 case X86::VMOVQI2PQIrm: in addConstantComments()
1980 case X86::VMOVQI2PQIZrm: in addConstantComments()
1984 MASK_AVX512_CASE(X86::VMOVSHZrm) in addConstantComments()
1985 case X86::VMOVSHZrm_alt: in addConstantComments()
1990 case X86::MOVSSrm: in addConstantComments()
1991 case X86::VMOVSSrm: in addConstantComments()
1992 MASK_AVX512_CASE(X86::VMOVSSZrm) in addConstantComments()
1993 case X86::MOVSSrm_alt: in addConstantComments()
1994 case X86::VMOVSSrm_alt: in addConstantComments()
1995 case X86::VMOVSSZrm_alt: in addConstantComments()
1996 case X86::MOVDI2PDIrm: in addConstantComments()
1997 case X86::VMOVDI2PDIrm: in addConstantComments()
1998 case X86::VMOVDI2PDIZrm: in addConstantComments()
2003 case X86::Prefix##MOVAPD##Suffix##rm: \ in addConstantComments()
2004 case X86::Prefix##MOVAPS##Suffix##rm: \ in addConstantComments()
2005 case X86::Prefix##MOVUPD##Suffix##rm: \ in addConstantComments()
2006 case X86::Prefix##MOVUPS##Suffix##rm: \ in addConstantComments()
2007 case X86::Prefix##MOVDQA##Suffix##rm: \ in addConstantComments()
2008 case X86::Prefix##MOVDQU##Suffix##rm: in addConstantComments()
2011 case X86::VMOVDQA64##Suffix##rm##Postfix: \ in addConstantComments()
2012 case X86::VMOVDQA32##Suffix##rm##Postfix: \ in addConstantComments()
2013 case X86::VMOVDQU64##Suffix##rm##Postfix: \ in addConstantComments()
2014 case X86::VMOVDQU32##Suffix##rm##Postfix: \ in addConstantComments()
2015 case X86::VMOVDQU16##Suffix##rm##Postfix: \ in addConstantComments()
2016 case X86::VMOVDQU8##Suffix##rm##Postfix: \ in addConstantComments()
2017 case X86::VMOVAPS##Suffix##rm##Postfix: \ in addConstantComments()
2018 case X86::VMOVAPD##Suffix##rm##Postfix: \ in addConstantComments()
2019 case X86::VMOVUPS##Suffix##rm##Postfix: \ in addConstantComments()
2020 case X86::VMOVUPD##Suffix##rm##Postfix: in addConstantComments()
2051 case X86::VBROADCASTF128rm: in addConstantComments()
2052 case X86::VBROADCASTI128rm: in addConstantComments()
2053 MASK_AVX512_CASE(X86::VBROADCASTF32X4Z256rm) in addConstantComments()
2054 MASK_AVX512_CASE(X86::VBROADCASTF64X2Z128rm) in addConstantComments()
2055 MASK_AVX512_CASE(X86::VBROADCASTI32X4Z256rm) in addConstantComments()
2056 MASK_AVX512_CASE(X86::VBROADCASTI64X2Z128rm) in addConstantComments()
2059 MASK_AVX512_CASE(X86::VBROADCASTF32X4rm) in addConstantComments()
2060 MASK_AVX512_CASE(X86::VBROADCASTF64X2rm) in addConstantComments()
2061 MASK_AVX512_CASE(X86::VBROADCASTI32X4rm) in addConstantComments()
2062 MASK_AVX512_CASE(X86::VBROADCASTI64X2rm) in addConstantComments()
2065 MASK_AVX512_CASE(X86::VBROADCASTF32X8rm) in addConstantComments()
2066 MASK_AVX512_CASE(X86::VBROADCASTF64X4rm) in addConstantComments()
2067 MASK_AVX512_CASE(X86::VBROADCASTI32X8rm) in addConstantComments()
2068 MASK_AVX512_CASE(X86::VBROADCASTI64X4rm) in addConstantComments()
2074 case X86::MOVDDUPrm: in addConstantComments()
2075 case X86::VMOVDDUPrm: in addConstantComments()
2076 MASK_AVX512_CASE(X86::VMOVDDUPZ128rm) in addConstantComments()
2077 case X86::VPBROADCASTQrm: in addConstantComments()
2078 MASK_AVX512_CASE(X86::VPBROADCASTQZ128rm) in addConstantComments()
2081 case X86::VBROADCASTSDYrm: in addConstantComments()
2082 MASK_AVX512_CASE(X86::VBROADCASTSDZ256rm) in addConstantComments()
2083 case X86::VPBROADCASTQYrm: in addConstantComments()
2084 MASK_AVX512_CASE(X86::VPBROADCASTQZ256rm) in addConstantComments()
2087 MASK_AVX512_CASE(X86::VBROADCASTSDZrm) in addConstantComments()
2088 MASK_AVX512_CASE(X86::VPBROADCASTQZrm) in addConstantComments()
2091 case X86::VBROADCASTSSrm: in addConstantComments()
2092 MASK_AVX512_CASE(X86::VBROADCASTSSZ128rm) in addConstantComments()
2093 case X86::VPBROADCASTDrm: in addConstantComments()
2094 MASK_AVX512_CASE(X86::VPBROADCASTDZ128rm) in addConstantComments()
2097 case X86::VBROADCASTSSYrm: in addConstantComments()
2098 MASK_AVX512_CASE(X86::VBROADCASTSSZ256rm) in addConstantComments()
2099 case X86::VPBROADCASTDYrm: in addConstantComments()
2100 MASK_AVX512_CASE(X86::VPBROADCASTDZ256rm) in addConstantComments()
2103 MASK_AVX512_CASE(X86::VBROADCASTSSZrm) in addConstantComments()
2104 MASK_AVX512_CASE(X86::VPBROADCASTDZrm) in addConstantComments()
2107 case X86::VPBROADCASTWrm: in addConstantComments()
2108 MASK_AVX512_CASE(X86::VPBROADCASTWZ128rm) in addConstantComments()
2111 case X86::VPBROADCASTWYrm: in addConstantComments()
2112 MASK_AVX512_CASE(X86::VPBROADCASTWZ256rm) in addConstantComments()
2115 MASK_AVX512_CASE(X86::VPBROADCASTWZrm) in addConstantComments()
2118 case X86::VPBROADCASTBrm: in addConstantComments()
2119 MASK_AVX512_CASE(X86::VPBROADCASTBZ128rm) in addConstantComments()
2122 case X86::VPBROADCASTBYrm: in addConstantComments()
2123 MASK_AVX512_CASE(X86::VPBROADCASTBZ256rm) in addConstantComments()
2126 MASK_AVX512_CASE(X86::VPBROADCASTBZrm) in addConstantComments()
2131 case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix: in addConstantComments()
2196 if (MI->getOpcode() == X86::OR64rm) { in emitInstruction()
2211 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_LEGACY) in emitInstruction()
2213 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) in emitInstruction()
2215 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_EVEX) in emitInstruction()
2223 case X86::EH_RETURN: in emitInstruction()
2224 case X86::EH_RETURN64: { in emitInstruction()
2231 case X86::CLEANUPRET: { in emitInstruction()
2237 case X86::CATCHRET: { in emitInstruction()
2243 case X86::ENDBR32: in emitInstruction()
2244 case X86::ENDBR64: { in emitInstruction()
2262 case X86::TAILJMPd64: in emitInstruction()
2263 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11)) in emitInstruction()
2264 EmitAndCountInstruction(MCInstBuilder(X86::CS_PREFIX)); in emitInstruction()
2266 case X86::TAILJMPr: in emitInstruction()
2267 case X86::TAILJMPm: in emitInstruction()
2268 case X86::TAILJMPd: in emitInstruction()
2269 case X86::TAILJMPd_CC: in emitInstruction()
2270 case X86::TAILJMPr64: in emitInstruction()
2271 case X86::TAILJMPm64: in emitInstruction()
2272 case X86::TAILJMPd64_CC: in emitInstruction()
2273 case X86::TAILJMPr64_REX: in emitInstruction()
2274 case X86::TAILJMPm64_REX: in emitInstruction()
2279 case X86::TLS_addr32: in emitInstruction()
2280 case X86::TLS_addr64: in emitInstruction()
2281 case X86::TLS_addrX32: in emitInstruction()
2282 case X86::TLS_base_addr32: in emitInstruction()
2283 case X86::TLS_base_addr64: in emitInstruction()
2284 case X86::TLS_base_addrX32: in emitInstruction()
2285 case X86::TLS_desc32: in emitInstruction()
2286 case X86::TLS_desc64: in emitInstruction()
2289 case X86::MOVPC32r: { in emitInstruction()
2301 MCInstBuilder(X86::CALLpcrel32) in emitInstruction()
2324 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg())); in emitInstruction()
2332 case X86::ADD32ri: { in emitInstruction()
2358 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri) in emitInstruction()
2397 case X86::MORESTACK_RET: in emitInstruction()
2401 case X86::KCFI_CHECK: in emitInstruction()
2404 case X86::ASAN_CHECK_MEMACCESS: in emitInstruction()
2407 case X86::MORESTACK_RET_RESTORE_R10: in emitInstruction()
2411 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX)); in emitInstruction()
2414 case X86::SEH_PushReg: in emitInstruction()
2415 case X86::SEH_SaveReg: in emitInstruction()
2416 case X86::SEH_SaveXMM: in emitInstruction()
2417 case X86::SEH_StackAlloc: in emitInstruction()
2418 case X86::SEH_StackAlign: in emitInstruction()
2419 case X86::SEH_SetFrame: in emitInstruction()
2420 case X86::SEH_PushFrame: in emitInstruction()
2421 case X86::SEH_EndPrologue: in emitInstruction()
2425 case X86::SEH_Epilogue: { in emitInstruction()
2437 EmitAndCountInstruction(MCInstBuilder(X86::NOOP)); in emitInstruction()
2443 case X86::UBSAN_UD1: in emitInstruction()
2444 EmitAndCountInstruction(MCInstBuilder(X86::UD1Lm) in emitInstruction()
2445 .addReg(X86::EAX) in emitInstruction()
2446 .addReg(X86::EAX) in emitInstruction()
2448 .addReg(X86::NoRegister) in emitInstruction()
2450 .addReg(X86::NoRegister)); in emitInstruction()
2452 case X86::CALL64pcrel32: in emitInstruction()
2453 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11)) in emitInstruction()
2454 EmitAndCountInstruction(MCInstBuilder(X86::CS_PREFIX)); in emitInstruction()
2456 case X86::JCC_1: in emitInstruction()
2468 EmitAndCountInstruction(MCInstBuilder(X86::DS_PREFIX)); in emitInstruction()