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/linux/Documentation/driver-api/md/
H A D	raid5-cache.rst	5 Raid 4/5/6 could include an extra disk for data cache besides normal RAID 7 caches data to the RAID disks. The cache can be in write-through (supported 8 since 4.4) or write-back mode (supported since 4.10). mdadm (supported since 9 3.4) has a new option '--write-journal' to create array with cache. Please 11 in write-through mode. A user can switch it to write-back mode by:: 13 echo "write-back" > /sys/block/md0/md/journal_mode 15 And switch it back to write-through mode by:: 17 echo "write-through" > /sys/block/md0/md/journal_mode 22 write-through mode 25 This mode mainly fixes the 'write hole' issue. For RAID 4/5/6 array, an unclean [all …]
H A D	raid5-ppl.rst	7 may become inconsistent with data on other member disks. If the array is also 9 disks is missing. This can lead to silent data corruption when rebuilding the 10 array or using it is as degraded - data calculated from parity for array blocks 11 that have not been touched by a write request during the unclean shutdown can 12 be incorrect. Such condition is known as the RAID5 Write Hole. Because of 15 Partial parity for a write operation is the XOR of stripe data chunks not 16 modified by this write. It is just enough data needed for recovering from the 17 write hole. XORing partial parity with the modified chunks produces parity for 18 the stripe, consistent with its state before the write operation, regardless of 19 which chunk writes have completed. If one of the not modified data disks of [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 10 "Unit": "CPU-M-CF", 14 …anslation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a … 17 "Unit": "CPU-M-CF", 21 …s for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress… 24 "Unit": "CPU-M-CF", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 31 "Unit": "CPU-M-CF", [all …]
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A D	macsec_api.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 48 /! Read the raw table data from the specified row of the Egress CTL 50 * rec - [OUT] The raw table row data will be unpacked into the fields of rec. 51 * table_index - The table row to read (max 23). 57 /! Pack the fields of rec, and write the packed data into the 59 rec - [IN] The bitfield values to write to the table row. 60 * table_index - The table row to write(max 23). 66 /! Read the raw table data from the specified row of the Egress 68 rec - [OUT] The raw table row data will be unpacked into the fields of rec. 69 * table_index - The table row to read (max 47). [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 10 "Unit": "CPU-M-CF", 14 …anslation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a … 17 "Unit": "CPU-M-CF", 21 …s for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress… 24 "Unit": "CPU-M-CF", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 31 "Unit": "CPU-M-CF", [all …]
/linux/Documentation/wmi/devices/
H A D	msi-wmi-platform.rst	1 .. SPDX-License-Identifier: GPL-2.0-or-later 4 MSI WMI Platform Features driver (msi-wmi-platform) 18 data using the `bmfdec <https://github.com/pali/bmfdec>`_ utility: 24 guid("{ABBC0F60-8EA1-11d1-00A0-C90629100000}")] 26 [WmiDataId(1), read, write, Description("16 bytes of data")] uint8 Bytes[16]; 31 guid("{ABBC0F63-8EA1-11d1-00A0-C90629100000}")] 33 [WmiDataId(1), read, write, Description("32 bytes of data")] uint8 Bytes[32]; 38 guid("{ABBC0F6E-8EA1-11d1-00A0-C90629100000}")] 43 [WmiMethodId(1), Implemented, read, write, Description("Return the contents of a package")] 44 void GetPackage([out, id(0)] Package Data); [all …]
/linux/drivers/iio/dac/
H A D	ad5446-spi.c	1 // SPDX-License-Identifier: GPL-2.0 19 struct spi_device spi = to_spi_device(st->dev); in ad5446_write() 21 st->d16 = cpu_to_be16(val); in ad5446_write() 23 return spi_write(spi, &st->d16, sizeof(st->d16)); in ad5446_write() 28 struct spi_device spi = to_spi_device(st->dev); in ad5660_write() 30 put_unaligned_be24(val, st->d24); in ad5660_write() 32 return spi_write(spi, st->d24, sizeof(st->d24)); in ad5660_write() 42 return -ENODEV; in ad5446_spi_probe() 44 return ad5446_probe(&spi->dev, id->name, chip_info); in ad5446_spi_probe() 57 .write = ad5446_write, [all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A D	st,stm32-fmc2-ebi-props.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Christophe Kerello <christophe.kerello@foss.st.com> 11 - Marek Vasut <marex@denx.de> 14 st,fmc2-ebi-cs-transaction-type: 25 8: Synchronous read synchronous write PSRAM. 26 9: Synchronous read asynchronous write PSRAM. 27 10: Synchronous read synchronous write NOR. [all …]`
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 10 "Unit": "CPU-M-CF", 14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 17 "Unit": "CPU-M-CF", 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	l1d_cache.json	4 …ion": "Counts level 1 data cache refills caused by speculatively executed load or store operations… 8 …data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs cac… 12 …write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty … 16 …"PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read o… 20 …Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in… 24 …data cache accesses generated by store operations. This event also counts accesses caused by a DC … 28 …nts level 1 data cache refills caused by speculatively executed load instructions where the memory… 32 …ts level 1 data cache refills caused by speculatively executed store instructions where the memory… 36 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches… 40 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l1d_cache.json	4 …ion": "Counts level 1 data cache refills caused by speculatively executed load or store operations… 8 …data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs cac… 12 …write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty … 16 …Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in… 20 …data cache accesses generated by store operations. This event also counts accesses caused by a DC … 24 …nts level 1 data cache refills caused by speculatively executed load instructions where the memory… 28 …ts level 1 data cache refills caused by speculatively executed store instructions where the memory… 32 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches… 36 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou… 40 …"PublicDescription": "Counts dirty cache line evictions from the level 1 data cache caused by a ne… [all …]
/linux/tools/perf/pmu-events/
H A D	empty-pmu-events.c	2 /* SPDX-License-Identifier: GPL-2.0 / 5 #include <pmu-events/pmu-events.h> 23 / offset=13 / "l1-dcache\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\000\000\000" 24 / offset=99 / "l1-dcach 2920 pmu_events_table__for_each_event_pmu(const struct pmu_events_table table,const struct pmu_table_entry * pmu,pmu_event_iter_fn fn,void * data) pmu_events_table__for_each_event_pmu() argument 2942 pmu_events_table__find_event_pmu(const struct pmu_events_table * table,const struct pmu_table_entry * pmu,const char * name,pmu_event_iter_fn fn,void * data) pmu_events_table__find_event_pmu() argument 2984 pmu_events_table__for_each_event(const struct pmu_events_table * table,struct perf_pmu * pmu,pmu_event_iter_fn fn,void * data) pmu_events_table__for_each_event() argument 3007 pmu_events_table__find_event(const struct pmu_events_table * table,struct perf_pmu * pmu,const char * name,pmu_event_iter_fn fn,void * data) pmu_events_table__find_event() argument 3046 pmu_metrics_table__for_each_metric_pmu(const struct pmu_metrics_table * table,const struct pmu_table_entry * pmu,pmu_metric_iter_fn fn,void * data) pmu_metrics_table__for_each_metric_pmu() argument 3068 pmu_metrics_table__find_metric_pmu(const struct pmu_metrics_table * table,const struct pmu_table_entry * pmu,const char * metric,pmu_metric_iter_fn fn,void * data) pmu_metrics_table__find_metric_pmu() argument 3109 pmu_metrics_table__for_each_metric(const struct pmu_metrics_table * table,pmu_metric_iter_fn fn,void * data) pmu_metrics_table__for_each_metric() argument 3127 pmu_metrics_table__find_metric(const struct pmu_metrics_table * table,struct perf_pmu * pmu,const char * metric,pmu_metric_iter_fn fn,void * data) pmu_metrics_table__find_metric() argument 3304 pmu_for_each_core_event(pmu_event_iter_fn fn,void * data) pmu_for_each_core_event() argument 3318 pmu_for_each_core_metric(pmu_metric_iter_fn fn,void * data) pmu_for_each_core_metric() argument 3342 pmu_for_each_sys_event(pmu_event_iter_fn fn,void * data) pmu_for_each_sys_event() argument 3356 pmu_for_each_sys_metric(pmu_metric_iter_fn fn,void * data) pmu_for_each_sys_metric() argument [all...]
/linux/Documentation/hid/
H A D	intel-thc-hid.rst	1 .. SPDX-License-Identifier: GPL-2.0 10 - A natively half-duplex Quad I/O capable SPI master 11 - Low latency I2C interface to support HIDI2C compliant devices 12 - A HW sequencer with RW DMA capability to system memory 18 Hardware sequencer within the THC is responsible for transferring (via DMA) data from touch devices 19 into system memory. A ring buffer is used to avoid data loss due to asynchronous nature of data 20 consumption (by host) in relation to data production (by touch device via DMA). 22 Unlike other common SPI/I2C controllers, THC handles the HID device data interrupt and reset 29 ------------------------------- 31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 10 "Unit": "CPU-M-CF", 14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a re… 17 "Unit": "CPU-M-CF", 21 …progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	3 "Unit": "CPU-M-CF", 7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 10 "Unit": "CPU-M-CF", 14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 17 "Unit": "CPU-M-CF", 21 …Description": "A directory write to the Level-1 Data cache directory where the returned cache line… 24 "Unit": "CPU-M-CF", 28 …ription": "A directory write to the Level-1 Instruction cache directory where the returned cache l… 31 "Unit": "CPU-M-CF", 35 …cription": "A directory write to the Level-1 Data cache directory where the returned cache line wa… [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 10 "Unit": "CPU-M-CF", 14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a re… 17 "Unit": "CPU-M-CF", 21 …progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	cache.json	102 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 105 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 108 …ption": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher… 111 …ption": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher… 114 …"PublicDescription": "L2 cache write streaming mode. This event counts for each cycle where the co… 117 …"BriefDescription": "L2 cache write streaming mode. This event counts for each cycle where the cor… 120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr… 123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry… 126 …data cache write streaming mode. This event counts for each cycle where the core is in write strea… 129 …data cache write streaming mode. This event counts for each cycle where the core is in write strea… [all …]
/linux/drivers/scsi/
H A D	sense_codes.h	1 /* SPDX-License-Identifier: GPL-2.0 / 4 http://www.t10.org/lists/asc-num.txt [most recent: 20200817] 9 SENSE_CODE(0x0002, "End-of-partition/medium detected") 11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected") 12 SENSE_CODE(0x0005, "End-of-data detected") 38 SENSE_CODE(0x0300, "Peripheral device write fault") 39 SENSE_CODE(0x0301, "No write current") 40 SENSE_CODE(0x0302, "Excessive write errors") 50 SENSE_CODE(0x0408, "Logical unit not ready, long write in progress") 51 SENSE_CODE(0x0409, "Logical unit not ready, self-test in progress") [all …]
/linux/include/uapi/linux/
H A D	virtio_pcidev.h	1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) / 11 enum virtio_pcidev_ops - virtual PCI device operations 14 * the @data field should be filled in by the device (in little endian). 15 * @VIRTIO_PCIDEV_OP_CFG_WRITE: write config space, size is 1, 2, 4 or 8; 16 * the @data field contains the data to write (in little endian). 18 * the @data field should be filled in by the device (in little endian). 19 * @VIRTIO_PCIDEV_OP_MMIO_WRITE: write BAR mem/pio, size can be variable; 20 * the @data field contains the data to write (in little endian). 22 * the @data field only has one byte (unlike @VIRTIO_PCIDEV_OP_MMIO_WRITE) 23 * @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	data-fabric.json	4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.", 12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.", 20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.", 28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.", 36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.", 44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.", 52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.", 60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.", 68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.", 76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.", [all …]
/linux/Documentation/filesystems/spufs/
H A D	spufs.rst	1 .. SPDX-License-Identifier: GPL-2.0 10 spufs - the SPU file system 21 message queues. Users that have write permissions on the file system 26 logical SPU. Users can change permissions on those files, but not actu- 43 The files in spufs mostly follow the standard behavior for regular sys- 44 tem calls like read(2) or write(2), but often support only a subset of 50 all files that support the write(2) operation also support writev(2). 55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera- 65 data in the address space of the SPU. The possible operations on an 68 read(2), pread(2), write(2), pwrite(2), lseek(2) [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A D	extended.json	3 "Unit": "CPU-M-CF", 7 …Description": "A directory write to the Level-1 Data Cache directory where the returned cache line… 10 "Unit": "CPU-M-CF", 14 …ription": "A directory write to the Level-1 Instruction Cache directory where the returned cache l… 17 "Unit": "CPU-M-CF", 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 "Unit": "CPU-M-CF", 28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 31 "Unit": "CPU-M-CF", 35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache." [all …]
/linux/net/ipv4/
H A D	sysctl_net_ipv4.c	1 // SPDX-License-Identifier: GPL-2.0 26 static int tcp_adv_win_scale_min = -31; 52 GENMASK_U8(ICMP_ERR_EXT_COUNT - 1, 0); 62 if (same_parity && !net->ipv4.ip_local_ports.warned) { in set_local_port_range() 63 net->ipv4.ip_local_ports.warned = true; in set_local_port_range() 66 WRITE_ONCE(net->ipv4.ip_local_ports.range, high << 16 \| low); in set_local_port_range() 70 static int ipv4_local_port_range(const struct ctl_table table, int write, in ipv4_local_port_range() argument 73 struct net net = table->data; in ipv4_local_port_range() 77 .data = &range, in ipv4_local_port_range() 79 .mode = table->mode, in ipv4_local_port_range() [all …]
/linux/drivers/misc/eeprom/
H A D	idt_89hpesx.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2016 T-Platforms. All Rights Reserved. 5 * IDT PCIe-switch NTB Linux driver 8 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru> 11 * NOTE of the IDT 89HPESx SMBus-slave interface driver 13 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO- 16 * binary sysfs-file in the device directory: 17 * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom 18 * In case if read-only flag is specified in the dts-node of device desription, 19 * User-space applications won't be able to write to the EEPROM sysfs-node. [all …]
/linux/Documentation/userspace-api/media/v4l/
H A D	func-write.rst	1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later 4 .. _func-write: 7 V4L2 write() 13 v4l2-write - Write to a V4L2 device 18 .. code-block:: c 22 .. c:function:: ssize_t write( int fd, void *buf, size_t count ) 31 Buffer with data to be written 39 :c:func:`write()` writes up to ``count`` bytes to the device 42 enables them. When ``count`` is zero, :c:func:`write()` returns 0 45 When the application does not provide more data in time, the previous [all …]

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