| /linux/arch/arm/include/asm/hardware/ |
| H A D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| /linux/arch/loongarch/include/asm/ |
| H A D | kvm_csr.h | 18 " gcsrrd %[val], %[reg]\n\t" \
19 : [val] "=r" (__v) \
29 " gcsrwr %[val], %[reg]\n\t" \
30 : [val] "+r" (__v) \
40 " gcsrxchg %[val], %[mask], %[reg]\n\t" \
41 : [val] "+r" (__v) \
49 #define write_gcsr_crmd(val) gcsr_write(val, LOONGARCH_CSR_CRMD) argument
51 #define write_gcsr_prmd(val) gcsr_write(val, LOONGARCH_CSR_PRMD) argument
53 #define write_gcsr_euen(val) gcsr_write(val, LOONGARCH_CSR_EUEN) argument
55 #define write_gcsr_misc(val) gcsr_write(val, LOONGARCH_CSR_MISC) argument
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| /linux/drivers/accel/ivpu/ |
| H A D | ivpu_hw_ip.c | 76 u32 val = 0; in host_ss_rst_clr() local
78 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in host_ss_rst_clr()
79 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in host_ss_rst_clr()
80 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in host_ss_rst_clr()
82 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in host_ss_rst_clr()
87 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_37xx() local
89 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_37xx()
97 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_40xx() local
99 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_40xx()
115 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_37xx() local
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| /linux/drivers/media/tuners/ |
| H A D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| H A D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /linux/drivers/phy/ |
| H A D | phy-xgene.c | 555 u32 val; in sds_wr() local
565 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
566 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
568 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
577 u32 val; in sds_rd() local
585 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
586 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
589 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
598 u32 val; in cmu_wr() local
607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_fixed.h | 15 u32 val; member
18 #define FP_16_16_MAX ((uint_fixed_16_16_t){ .val = UINT_MAX })
20 static inline bool is_fixed16_zero(uint_fixed_16_16_t val) in is_fixed16_zero() argument
22 return val.val == 0; in is_fixed16_zero()
25 static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) in u32_to_fixed16() argument
27 uint_fixed_16_16_t fp = { .val = val << 16 }; in u32_to_fixed16()
29 WARN_ON(val > U16_MAX); in u32_to_fixed16()
36 return DIV_ROUND_UP(fp.val, 1 << 16); in fixed16_to_u32_round_up()
41 return fp.val >> 16; in fixed16_to_u32()
47 uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) }; in min_fixed16()
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| /linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask); member
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos() argument
48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag() argument
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
64 f->val.frag = 1; in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto() argument
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip() argument
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| /linux/tools/perf/util/ |
| H A D | expr.y | 40 double val;
75 /* During computing ids, does val represent a constant (non-BOTTOM) value? */
76 static bool is_const(double val)
78 return isfinite(val);
84 .val = BOTTOM,
102 result.val = NAN;
104 result.val = source_count
115 result.val = BOTTOM;
131 if (!compute_ids || (is_const(LHS.val) && is_const(RHS.val))) { \
134 if (isnan(LHS.val) || isnan(RHS.val)) { \
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| /linux/include/sound/ |
| H A D | emu8000_reg.h | 108 #define EMU8000_CPF_WRITE(emu, chan, val) \ argument
109 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
110 #define EMU8000_PTRX_WRITE(emu, chan, val) \ argument
111 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
112 #define EMU8000_CVCF_WRITE(emu, chan, val) \ argument
113 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
114 #define EMU8000_VTFT_WRITE(emu, chan, val) \ argument
115 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
116 #define EMU8000_PSST_WRITE(emu, chan, val) \ argument
117 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
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| /linux/drivers/usb/phy/ |
| H A D | phy-tegra-usb.c | 224 u32 val; in set_pts() local
227 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
228 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); in set_pts()
229 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); in set_pts()
230 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
232 val = readl_relaxed(base + TEGRA_USB_PORTSC1); in set_pts()
233 val &= ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
234 val &= ~TEGRA_USB_PORTSC1_PTS(~0); in set_pts()
235 val |= TEGRA_USB_PORTSC1_PTS(pts_val); in set_pts()
236 writel_relaxed(val, base + TEGRA_USB_PORTSC1); in set_pts()
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| /linux/drivers/net/phy/mscc/ |
| H A D | mscc_ptp.c | 27 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_ts_base_write() argument
33 val); in phy_ts_base_write()
67 u32 val, cnt = 0; in vsc85xx_ts_read_csr() local
92 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); in vsc85xx_ts_read_csr()
93 } while (!(val & BIU_ADDR_EXE) && cnt++ < BIU_ADDR_CNT_MAX); in vsc85xx_ts_read_csr()
95 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB); in vsc85xx_ts_read_csr()
96 val <<= 16; in vsc85xx_ts_read_csr()
97 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB); in vsc85xx_ts_read_csr()
103 return val; in vsc85xx_ts_read_csr()
107 u16 addr, u32 val) in vsc85xx_ts_write_csr() argument
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| /linux/arch/s390/include/asm/ |
| H A D | percpu.h | 28 #define arch_this_cpu_to_op_simple(pcp, val, op) \ argument
38 new__ = old__ op (val); \
45 #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
46 #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
47 #define this_cpu_add_return_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
48 #define this_cpu_add_return_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
49 #define this_cpu_and_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
50 #define this_cpu_and_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
51 #define this_cpu_or_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
52 #define this_cpu_or_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
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| /linux/arch/mips/pci/ |
| H A D | pci-bcm63xx.c | 109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel()
123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie()
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
166 val |= OPT1_RD_REPLY_BE_FIX_EN; in bcm63xx_register_pcie()
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| /linux/drivers/net/wireless/ath/ath5k/ |
| H A D | eeprom.c | 43 u16 val; in ath5k_eeprom_bin2freq() local
50 val = (5 * bin) + 4800; in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
56 val = bin + 2300; in ath5k_eeprom_bin2freq()
58 val = bin + 2400; in ath5k_eeprom_bin2freq()
61 return val; in ath5k_eeprom_bin2freq()
76 u16 val; in ath5k_eeprom_init_header() local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); in ath5k_eeprom_init_header()
97 if (val) { in ath5k_eeprom_init_header()
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << in ath5k_eeprom_init_header()
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| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-cp110-comphy.c | 340 u32 val; in mvebu_comphy_ethernet_init_reset() local
342 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); in mvebu_comphy_ethernet_init_reset()
343 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; in mvebu_comphy_ethernet_init_reset()
344 val |= MVEBU_COMPHY_CONF1_PWRUP; in mvebu_comphy_ethernet_init_reset()
345 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); in mvebu_comphy_ethernet_init_reset()
348 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
349 val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL | in mvebu_comphy_ethernet_init_reset()
359 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | in mvebu_comphy_ethernet_init_reset()
363 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xb) | in mvebu_comphy_ethernet_init_reset()
368 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) | in mvebu_comphy_ethernet_init_reset()
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| /linux/sound/soc/hisilicon/ |
| H A D | hi6210-i2s.c | 80 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val) in hi6210_write_reg() argument
82 writel(val, i2s->base + reg); in hi6210_write_reg()
95 u32 val; in hi6210_i2s_startup() local
98 regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val); in hi6210_i2s_startup()
99 if (val & BIT(4)) in hi6210_i2s_startup()
126 val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK); in hi6210_i2s_startup()
127 val |= 0x3f; in hi6210_i2s_startup()
128 hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val); in hi6210_i2s_startup()
132 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1); in hi6210_i2s_startup()
133 val |= (BIT(5) | BIT(4)); in hi6210_i2s_startup()
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| /linux/drivers/net/phy/ |
| H A D | phy-c45.c | 19 int val; in genphy_c45_baset1_able() local
22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_baset1_able()
23 if (val < 0) in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
399 int val; in genphy_c45_aneg_done() local
404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
406 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; in genphy_c45_aneg_done()
421 int val, devad; in genphy_c45_read_link() local
425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
426 if (val < 0) in genphy_c45_read_link()
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| /linux/include/asm-generic/ |
| H A D | percpu.h | 70 #define raw_cpu_generic_to_op(pcp, val, op) \ argument
72 *raw_cpu_ptr(&(pcp)) op val; \
75 #define raw_cpu_generic_add_return(pcp, val) \ argument
79 *__p += val; \
152 #define this_cpu_generic_to_op(pcp, val, op) \ argument
156 raw_cpu_generic_to_op(pcp, val, op); \
161 #define this_cpu_generic_add_return(pcp, val) \ argument
166 __ret = raw_cpu_generic_add_return(pcp, val); \
215 #define raw_cpu_write_1(pcp, val) raw_cpu_generic_to_op(pcp, val, =) argument
218 #define raw_cpu_write_2(pcp, val) raw_cpu_generic_to_op(pcp, val, =) argument
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| /linux/drivers/phy/socionext/ |
| H A D | phy-uniphier-ahci.c | 76 u32 val; in uniphier_ahciphy_pro4_init() local
79 val = readl(priv->base + CKCTRL0); in uniphier_ahciphy_pro4_init()
80 val &= ~CKCTRL0_NCY_MASK; in uniphier_ahciphy_pro4_init()
81 val |= FIELD_PREP(CKCTRL0_NCY_MASK, 0x6); in uniphier_ahciphy_pro4_init()
82 val &= ~CKCTRL0_NCY5_MASK; in uniphier_ahciphy_pro4_init()
83 val |= FIELD_PREP(CKCTRL0_NCY5_MASK, 0x2); in uniphier_ahciphy_pro4_init()
84 val &= ~CKCTRL0_PRESCALE_MASK; in uniphier_ahciphy_pro4_init()
85 val |= FIELD_PREP(CKCTRL0_PRESCALE_MASK, 0x1); in uniphier_ahciphy_pro4_init()
86 writel(val, priv->base + CKCTRL0); in uniphier_ahciphy_pro4_init()
89 val = readl(priv->base + CKCTRL1); in uniphier_ahciphy_pro4_init()
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| /linux/drivers/gpu/drm/sprd/ |
| H A D | megacores_pll.c | 127 static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[]) in dphy_set_timing_reg() argument
131 regmap_write(regmap, 0x31, val[CLK]); in dphy_set_timing_reg()
132 regmap_write(regmap, 0x41, val[DATA]); in dphy_set_timing_reg()
133 regmap_write(regmap, 0x51, val[DATA]); in dphy_set_timing_reg()
134 regmap_write(regmap, 0x61, val[DATA]); in dphy_set_timing_reg()
135 regmap_write(regmap, 0x71, val[DATA]); in dphy_set_timing_reg()
137 regmap_write(regmap, 0x90, val[CLK]); in dphy_set_timing_reg()
138 regmap_write(regmap, 0xa0, val[DATA]); in dphy_set_timing_reg()
139 regmap_write(regmap, 0xb0, val[DATA]); in dphy_set_timing_reg()
140 regmap_write(regmap, 0xc0, val[DATA]); in dphy_set_timing_reg()
[all …]
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| /linux/drivers/media/platform/qcom/camss/ |
| H A D | camss-csid-gen2.c | 183 int val; in __csid_configure_rx() local
188 val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; in __csid_configure_rx()
189 val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; in __csid_configure_rx()
190 val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL; in __csid_configure_rx()
191 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); in __csid_configure_rx()
193 val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; in __csid_configure_rx()
195 val |= 1 << CSI2_RX_CFG1_VC_MODE; in __csid_configure_rx()
196 val |= 1 << CSI2_RX_CFG1_MISR_EN; in __csid_configure_rx()
197 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); in __csid_configure_rx()
202 int val; in __csid_ctrl_rdi() local
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| /linux/drivers/power/supply/ |
| H A D | lenovo_yoga_c630_battery.c | 74 int val; in yoga_c630_psy_update_bat_info() local
78 val = yoga_c630_ec_read8(ec, LENOVO_EC_BAT_PRESENT); in yoga_c630_psy_update_bat_info()
79 if (val < 0) in yoga_c630_psy_update_bat_info()
80 return val; in yoga_c630_psy_update_bat_info()
81 ecbat->bat_present = !!(val & LENOVO_EC_BAT_PRESENT_IS_PRESENT); in yoga_c630_psy_update_bat_info()
83 return val; in yoga_c630_psy_update_bat_info()
85 val = yoga_c630_ec_read8(ec, LENOVO_EC_BAT_ATTRIBUTES); in yoga_c630_psy_update_bat_info()
86 if (val < 0) in yoga_c630_psy_update_bat_info()
87 return val; in yoga_c630_psy_update_bat_info()
88 ecbat->unit_mA = val & LENOVO_EC_BAT_ATTRIBUTES_UNIT_IS_MA; in yoga_c630_psy_update_bat_info()
[all …]
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| /linux/sound/pci/ac97/ |
| H A D | ac97_proc.c | 95 unsigned short val, tmp, ext, mext; in snd_ac97_proc_read_main() local
115 val = snd_ac97_read(ac97, AC97_INT_PAGING); in snd_ac97_proc_read_main()
126 AC97_PAGE_MASK, val & AC97_PAGE_MASK); in snd_ac97_proc_read_main()
129 // val = snd_ac97_read(ac97, AC97_RESET); in snd_ac97_proc_read_main()
130 val = ac97->caps; in snd_ac97_proc_read_main()
132 val & AC97_BC_DEDICATED_MIC ? " -dedicated MIC PCM IN channel-" : "", in snd_ac97_proc_read_main()
133 val & AC97_BC_RESERVED1 ? " -reserved1-" : "", in snd_ac97_proc_read_main()
134 val & AC97_BC_BASS_TREBLE ? " -bass & treble-" : "", in snd_ac97_proc_read_main()
135 val & AC97_BC_SIM_STEREO ? " -simulated stereo-" : "", in snd_ac97_proc_read_main()
136 val & AC97_BC_HEADPHONE ? " -headphone out-" : "", in snd_ac97_proc_read_main()
[all …]
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