224 	u32 val;  in set_pts()  local
227 		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);  in set_pts()
228 		val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);  in set_pts()
229 		val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);  in set_pts()
230 		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);  in set_pts()
232 		val = readl_relaxed(base + TEGRA_USB_PORTSC1);  in set_pts()
233 		val &= ~TEGRA_PORTSC1_RWC_BITS;  in set_pts()
234 		val &= ~TEGRA_USB_PORTSC1_PTS(~0);  in set_pts()
235 		val |= TEGRA_USB_PORTSC1_PTS(pts_val);  in set_pts()
236 		writel_relaxed(val, base + TEGRA_USB_PORTSC1);  in set_pts()
243 	u32 val;  in set_phcd()  local
246 		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);  in set_phcd()
248 			val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;  in set_phcd()
250 			val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;  in set_phcd()
251 		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);  in set_phcd()
253 		val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;  in set_phcd()
255 			val |= TEGRA_USB_PORTSC1_PHCD;  in set_phcd()
257 			val &= ~TEGRA_USB_PORTSC1_PHCD;  in set_phcd()
258 		writel_relaxed(val, base + TEGRA_USB_PORTSC1);  in set_phcd()
330 	u32 val;  in utmip_pad_power_on()  local
340 		val = readl_relaxed(base + UTMIP_BIAS_CFG0);  in utmip_pad_power_on()
341 		val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);  in utmip_pad_power_on()
344 			val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |  in utmip_pad_power_on()
348 			val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);  in utmip_pad_power_on()
349 			val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);  in utmip_pad_power_on()
350 			val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);  in utmip_pad_power_on()
352 		writel_relaxed(val, base + UTMIP_BIAS_CFG0);  in utmip_pad_power_on()
370 	u32 val;  in utmip_pad_power_off()  local
397 		val = readl_relaxed(base + UTMIP_BIAS_CFG0);  in utmip_pad_power_off()
398 		val |= UTMIP_OTGPD | UTMIP_BIASPD;  in utmip_pad_power_off()
399 		writel_relaxed(val, base + UTMIP_BIAS_CFG0);  in utmip_pad_power_off()
420 	u32 val;  in utmi_phy_clk_disable()  local
431 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
432 		val |= USB_SUSP_SET;  in utmi_phy_clk_disable()
433 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
437 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
438 		val &= ~USB_SUSP_SET;  in utmi_phy_clk_disable()
439 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
452 	u32 val;  in utmi_phy_clk_enable()  local
464 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
465 		val |= USB_SUSP_CLR;  in utmi_phy_clk_enable()
466 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
470 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
471 		val &= ~USB_SUSP_CLR;  in utmi_phy_clk_enable()
472 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
487 	u32 val;  in utmi_phy_power_on()  local
490 	val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
491 	val |= UTMIP_RESET;  in utmi_phy_power_on()
492 	writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
495 		val = readl_relaxed(base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
496 		val |= USB1_NO_LEGACY_MODE;  in utmi_phy_power_on()
497 		writel_relaxed(val, base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
500 	val = readl_relaxed(base + UTMIP_TX_CFG0);  in utmi_phy_power_on()
501 	val |= UTMIP_FS_PREABMLE_J;  in utmi_phy_power_on()
502 	writel_relaxed(val, base + UTMIP_TX_CFG0);  in utmi_phy_power_on()
504 	val = readl_relaxed(base + UTMIP_HSRX_CFG0);  in utmi_phy_power_on()
505 	val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));  in utmi_phy_power_on()
506 	val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);  in utmi_phy_power_on()
507 	val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);  in utmi_phy_power_on()
508 	writel_relaxed(val, base + UTMIP_HSRX_CFG0);  in utmi_phy_power_on()
510 	val = readl_relaxed(base + UTMIP_HSRX_CFG1);  in utmi_phy_power_on()
511 	val &= ~UTMIP_HS_SYNC_START_DLY(~0);  in utmi_phy_power_on()
512 	val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);  in utmi_phy_power_on()
513 	writel_relaxed(val, base + UTMIP_HSRX_CFG1);  in utmi_phy_power_on()
515 	val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);  in utmi_phy_power_on()
516 	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);  in utmi_phy_power_on()
517 	val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);  in utmi_phy_power_on()
518 	writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);  in utmi_phy_power_on()
520 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_power_on()
521 	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;  in utmi_phy_power_on()
522 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_power_on()
525 		val = readl_relaxed(base + UTMIP_MISC_CFG1);  in utmi_phy_power_on()
526 		val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |  in utmi_phy_power_on()
528 		val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |  in utmi_phy_power_on()
530 		writel_relaxed(val, base + UTMIP_MISC_CFG1);  in utmi_phy_power_on()
532 		val = readl_relaxed(base + UTMIP_PLL_CFG1);  in utmi_phy_power_on()
533 		val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |  in utmi_phy_power_on()
535 		val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |  in utmi_phy_power_on()
537 		writel_relaxed(val, base + UTMIP_PLL_CFG1);  in utmi_phy_power_on()
540 	val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
541 	val &= ~USB_WAKE_ON_RESUME_EN;  in utmi_phy_power_on()
542 	writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
545 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
546 		val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);  in utmi_phy_power_on()
547 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
549 		val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);  in utmi_phy_power_on()
550 		val &= ~VBUS_WAKEUP_WAKEUP_EN;  in utmi_phy_power_on()
551 		val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);  in utmi_phy_power_on()
552 		writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);  in utmi_phy_power_on()
554 		val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);  in utmi_phy_power_on()
555 		val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN);  in utmi_phy_power_on()
556 		val &= ~(B_SESS_VLD_WAKEUP_EN);  in utmi_phy_power_on()
557 		writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);  in utmi_phy_power_on()
559 		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
560 		val &= ~UTMIP_PD_CHRG;  in utmi_phy_power_on()
561 		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
563 		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
564 		val |= UTMIP_PD_CHRG;  in utmi_phy_power_on()
565 		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
572 	val = readl_relaxed(base + UTMIP_XCVR_CFG0);  in utmi_phy_power_on()
573 	val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |  in utmi_phy_power_on()
579 		val |= UTMIP_XCVR_SETUP(config->xcvr_setup);  in utmi_phy_power_on()
580 		val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);  in utmi_phy_power_on()
582 	val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);  in utmi_phy_power_on()
583 	val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);  in utmi_phy_power_on()
586 		val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));  in utmi_phy_power_on()
587 		val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);  in utmi_phy_power_on()
588 		val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);  in utmi_phy_power_on()
590 	writel_relaxed(val, base + UTMIP_XCVR_CFG0);  in utmi_phy_power_on()
592 	val = readl_relaxed(base + UTMIP_XCVR_CFG1);  in utmi_phy_power_on()
593 	val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |  in utmi_phy_power_on()
595 	val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);  in utmi_phy_power_on()
596 	writel_relaxed(val, base + UTMIP_XCVR_CFG1);  in utmi_phy_power_on()
598 	val = readl_relaxed(base + UTMIP_BIAS_CFG1);  in utmi_phy_power_on()
599 	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);  in utmi_phy_power_on()
600 	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);  in utmi_phy_power_on()
601 	writel_relaxed(val, base + UTMIP_BIAS_CFG1);  in utmi_phy_power_on()
603 	val = readl_relaxed(base + UTMIP_SPARE_CFG0);  in utmi_phy_power_on()
605 		val |= FUSE_SETUP_SEL;  in utmi_phy_power_on()
607 		val &= ~FUSE_SETUP_SEL;  in utmi_phy_power_on()
608 	writel_relaxed(val, base + UTMIP_SPARE_CFG0);  in utmi_phy_power_on()
611 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
612 		val |= UTMIP_PHY_ENABLE;  in utmi_phy_power_on()
613 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
616 	val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
617 	val &= ~UTMIP_RESET;  in utmi_phy_power_on()
618 	writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
621 		val = readl_relaxed(base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
622 		val &= ~USB1_VBUS_SENSE_CTL_MASK;  in utmi_phy_power_on()
623 		val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;  in utmi_phy_power_on()
624 		writel_relaxed(val, base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
626 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
627 		val &= ~USB_SUSP_SET;  in utmi_phy_power_on()
628 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
634 		val = readl_relaxed(base + USB_USBMODE);  in utmi_phy_power_on()
635 		val &= ~USB_USBMODE_MASK;  in utmi_phy_power_on()
637 			val |= USB_USBMODE_HOST;  in utmi_phy_power_on()
639 			val |= USB_USBMODE_DEVICE;  in utmi_phy_power_on()
640 		writel_relaxed(val, base + USB_USBMODE);  in utmi_phy_power_on()
652 	u32 val;  in utmi_phy_power_off()  local
660 					   val, !(val & VBUS_WAKEUP_STS),  in utmi_phy_power_off()
667 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_off()
668 		val |= UTMIP_RESET;  in utmi_phy_power_off()
669 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_off()
672 	val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_off()
673 	val |= UTMIP_PD_CHRG;  in utmi_phy_power_off()
674 	writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_off()
677 		val = readl_relaxed(base + UTMIP_XCVR_CFG0);  in utmi_phy_power_off()
678 		val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |  in utmi_phy_power_off()
680 		writel_relaxed(val, base + UTMIP_XCVR_CFG0);  in utmi_phy_power_off()
683 	val = readl_relaxed(base + UTMIP_XCVR_CFG1);  in utmi_phy_power_off()
684 	val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |  in utmi_phy_power_off()
686 	writel_relaxed(val, base + UTMIP_XCVR_CFG1);  in utmi_phy_power_off()
689 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_off()
690 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);  in utmi_phy_power_off()
691 		val |= USB_WAKEUP_DEBOUNCE_COUNT(5);  in utmi_phy_power_off()
692 		val |= USB_WAKE_ON_RESUME_EN;  in utmi_phy_power_off()
693 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_off()
700 			val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);  in utmi_phy_power_off()
701 			val |= VBUS_WAKEUP_WAKEUP_EN;  in utmi_phy_power_off()
702 			val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);  in utmi_phy_power_off()
703 			writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);  in utmi_phy_power_off()
705 			val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);  in utmi_phy_power_off()
706 			val |= A_VBUS_VLD_WAKEUP_EN;  in utmi_phy_power_off()
707 			writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);  in utmi_phy_power_off()
717 	u32 val;  in utmi_phy_preresume()  local
719 	val = readl_relaxed(base + UTMIP_TX_CFG0);  in utmi_phy_preresume()
720 	val |= UTMIP_HS_DISCON_DISABLE;  in utmi_phy_preresume()
721 	writel_relaxed(val, base + UTMIP_TX_CFG0);  in utmi_phy_preresume()
727 	u32 val;  in utmi_phy_postresume()  local
729 	val = readl_relaxed(base + UTMIP_TX_CFG0);  in utmi_phy_postresume()
730 	val &= ~UTMIP_HS_DISCON_DISABLE;  in utmi_phy_postresume()
731 	writel_relaxed(val, base + UTMIP_TX_CFG0);  in utmi_phy_postresume()
738 	u32 val;  in utmi_phy_restore_start()  local
740 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
741 	val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);  in utmi_phy_restore_start()
743 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;  in utmi_phy_restore_start()
745 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;  in utmi_phy_restore_start()
746 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
749 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
750 	val |= UTMIP_DPDM_OBSERVE;  in utmi_phy_restore_start()
751 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
758 	u32 val;  in utmi_phy_restore_end()  local
760 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_end()
761 	val &= ~UTMIP_DPDM_OBSERVE;  in utmi_phy_restore_end()
762 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_end()
769 	u32 val;  in ulpi_phy_power_on()  local
784 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
785 	val |= UHSIC_RESET;  in ulpi_phy_power_on()
786 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
788 	val = readl_relaxed(base + ULPI_TIMING_CTRL_0);  in ulpi_phy_power_on()
789 	val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;  in ulpi_phy_power_on()
790 	writel_relaxed(val, base + ULPI_TIMING_CTRL_0);  in ulpi_phy_power_on()
792 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
793 	val |= ULPI_PHY_ENABLE;  in ulpi_phy_power_on()
794 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
796 	val = 0;  in ulpi_phy_power_on()
797 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
799 	val |= ULPI_DATA_TRIMMER_SEL(4);  in ulpi_phy_power_on()
800 	val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);  in ulpi_phy_power_on()
801 	val |= ULPI_DIR_TRIMMER_SEL(4);  in ulpi_phy_power_on()
802 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
805 	val |= ULPI_DATA_TRIMMER_LOAD;  in ulpi_phy_power_on()
806 	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;  in ulpi_phy_power_on()
807 	val |= ULPI_DIR_TRIMMER_LOAD;  in ulpi_phy_power_on()
808 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
823 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
824 	val |= USB_SUSP_CLR;  in ulpi_phy_power_on()
825 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
828 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
829 	val &= ~USB_SUSP_CLR;  in ulpi_phy_power_on()
830 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
920 	u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET;  in tegra_usb_phy_isr()  local
929 	val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);  in tegra_usb_phy_isr()
930 	writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);  in tegra_usb_phy_isr()
932 	return val & int_mask ? IRQ_HANDLED : IRQ_NONE;  in tegra_usb_phy_isr()
940 	u32 val;  in tegra_usb_phy_set_wakeup()  local
946 		val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);  in tegra_usb_phy_set_wakeup()
947 		val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN);  in tegra_usb_phy_set_wakeup()
948 		writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);  in tegra_usb_phy_set_wakeup()
968 			val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);  in tegra_usb_phy_set_wakeup()
969 			val |= ID_INT_EN | VBUS_WAKEUP_INT_EN;  in tegra_usb_phy_set_wakeup()
970 			writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);  in tegra_usb_phy_set_wakeup()
1016 	int err, val = 0;  in tegra_usb_phy_configure_pmc()  local
1032 		val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4;  in tegra_usb_phy_configure_pmc()
1036 		val |= ID_PD_P0 << phy->instance * 4;  in tegra_usb_phy_configure_pmc()
1039 	err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val);  in tegra_usb_phy_configure_pmc()
1048 	err = regmap_clear_bits(phy->pmc_regmap, PMC_USB_AO, val);  in tegra_usb_phy_configure_pmc()