1e7300d04SMaxime Bizon /*
2e7300d04SMaxime Bizon * This file is subject to the terms and conditions of the GNU General Public
3e7300d04SMaxime Bizon * License. See the file "COPYING" in the main directory of this archive
4e7300d04SMaxime Bizon * for more details.
5e7300d04SMaxime Bizon *
6e7300d04SMaxime Bizon * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7e7300d04SMaxime Bizon */
8e7300d04SMaxime Bizon
9e7300d04SMaxime Bizon #include <linux/types.h>
10e7300d04SMaxime Bizon #include <linux/pci.h>
11e7300d04SMaxime Bizon #include <linux/kernel.h>
12e7300d04SMaxime Bizon #include <linux/init.h>
1319c860d9SJonas Gorski #include <linux/delay.h>
14f2d1035eSJonas Gorski #include <linux/clk.h>
15e7300d04SMaxime Bizon #include <asm/bootinfo.h>
16e7300d04SMaxime Bizon
17ba00e2e5SJonas Gorski #include <bcm63xx_reset.h>
18ba00e2e5SJonas Gorski
19e7300d04SMaxime Bizon #include "pci-bcm63xx.h"
20e7300d04SMaxime Bizon
21e7300d04SMaxime Bizon /*
22e7300d04SMaxime Bizon * Allow PCI to be disabled at runtime depending on board nvram
23e7300d04SMaxime Bizon * configuration
24e7300d04SMaxime Bizon */
25e7300d04SMaxime Bizon int bcm63xx_pci_enabled;
26e7300d04SMaxime Bizon
27e7300d04SMaxime Bizon static struct resource bcm_pci_mem_resource = {
28e7300d04SMaxime Bizon .name = "bcm63xx PCI memory space",
29e7300d04SMaxime Bizon .start = BCM_PCI_MEM_BASE_PA,
30e7300d04SMaxime Bizon .end = BCM_PCI_MEM_END_PA,
31e7300d04SMaxime Bizon .flags = IORESOURCE_MEM
32e7300d04SMaxime Bizon };
33e7300d04SMaxime Bizon
34e7300d04SMaxime Bizon static struct resource bcm_pci_io_resource = {
35e7300d04SMaxime Bizon .name = "bcm63xx PCI IO space",
36e7300d04SMaxime Bizon .start = BCM_PCI_IO_BASE_PA,
37e7300d04SMaxime Bizon #ifdef CONFIG_CARDBUS
38e7300d04SMaxime Bizon .end = BCM_PCI_IO_HALF_PA,
39e7300d04SMaxime Bizon #else
40e7300d04SMaxime Bizon .end = BCM_PCI_IO_END_PA,
41e7300d04SMaxime Bizon #endif
42e7300d04SMaxime Bizon .flags = IORESOURCE_IO
43e7300d04SMaxime Bizon };
44e7300d04SMaxime Bizon
45e7300d04SMaxime Bizon struct pci_controller bcm63xx_controller = {
46e7300d04SMaxime Bizon .pci_ops = &bcm63xx_pci_ops,
47e7300d04SMaxime Bizon .io_resource = &bcm_pci_io_resource,
48e7300d04SMaxime Bizon .mem_resource = &bcm_pci_mem_resource,
49e7300d04SMaxime Bizon };
50e7300d04SMaxime Bizon
51e7300d04SMaxime Bizon /*
52e7300d04SMaxime Bizon * We handle cardbus via a fake Cardbus bridge, memory and io spaces
53e7300d04SMaxime Bizon * have to be clearly separated from PCI one since we have different
54e7300d04SMaxime Bizon * memory decoder.
55e7300d04SMaxime Bizon */
56e7300d04SMaxime Bizon #ifdef CONFIG_CARDBUS
57e7300d04SMaxime Bizon static struct resource bcm_cb_mem_resource = {
58e7300d04SMaxime Bizon .name = "bcm63xx Cardbus memory space",
59e7300d04SMaxime Bizon .start = BCM_CB_MEM_BASE_PA,
60e7300d04SMaxime Bizon .end = BCM_CB_MEM_END_PA,
61e7300d04SMaxime Bizon .flags = IORESOURCE_MEM
62e7300d04SMaxime Bizon };
63e7300d04SMaxime Bizon
64e7300d04SMaxime Bizon static struct resource bcm_cb_io_resource = {
65e7300d04SMaxime Bizon .name = "bcm63xx Cardbus IO space",
66e7300d04SMaxime Bizon .start = BCM_PCI_IO_HALF_PA + 1,
67e7300d04SMaxime Bizon .end = BCM_PCI_IO_END_PA,
68e7300d04SMaxime Bizon .flags = IORESOURCE_IO
69e7300d04SMaxime Bizon };
70e7300d04SMaxime Bizon
71e7300d04SMaxime Bizon struct pci_controller bcm63xx_cb_controller = {
72e7300d04SMaxime Bizon .pci_ops = &bcm63xx_cb_ops,
73e7300d04SMaxime Bizon .io_resource = &bcm_cb_io_resource,
74e7300d04SMaxime Bizon .mem_resource = &bcm_cb_mem_resource,
75e7300d04SMaxime Bizon };
76e7300d04SMaxime Bizon #endif
77e7300d04SMaxime Bizon
7819c860d9SJonas Gorski static struct resource bcm_pcie_mem_resource = {
7919c860d9SJonas Gorski .name = "bcm63xx PCIe memory space",
8019c860d9SJonas Gorski .start = BCM_PCIE_MEM_BASE_PA,
8119c860d9SJonas Gorski .end = BCM_PCIE_MEM_END_PA,
8219c860d9SJonas Gorski .flags = IORESOURCE_MEM,
8319c860d9SJonas Gorski };
8419c860d9SJonas Gorski
8519c860d9SJonas Gorski static struct resource bcm_pcie_io_resource = {
8619c860d9SJonas Gorski .name = "bcm63xx PCIe IO space",
8719c860d9SJonas Gorski .start = 0,
8819c860d9SJonas Gorski .end = 0,
8919c860d9SJonas Gorski .flags = 0,
9019c860d9SJonas Gorski };
9119c860d9SJonas Gorski
9219c860d9SJonas Gorski struct pci_controller bcm63xx_pcie_controller = {
9319c860d9SJonas Gorski .pci_ops = &bcm63xx_pcie_ops,
9419c860d9SJonas Gorski .io_resource = &bcm_pcie_io_resource,
9519c860d9SJonas Gorski .mem_resource = &bcm_pcie_mem_resource,
9619c860d9SJonas Gorski };
9719c860d9SJonas Gorski
bcm63xx_int_cfg_readl(u32 reg)98e7300d04SMaxime Bizon static u32 bcm63xx_int_cfg_readl(u32 reg)
99e7300d04SMaxime Bizon {
100e7300d04SMaxime Bizon u32 tmp;
101e7300d04SMaxime Bizon
102e7300d04SMaxime Bizon tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
103e7300d04SMaxime Bizon tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
104e7300d04SMaxime Bizon bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
105e7300d04SMaxime Bizon iob();
106e7300d04SMaxime Bizon return bcm_mpi_readl(MPI_PCICFGDATA_REG);
107e7300d04SMaxime Bizon }
108e7300d04SMaxime Bizon
bcm63xx_int_cfg_writel(u32 val,u32 reg)109e7300d04SMaxime Bizon static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
110e7300d04SMaxime Bizon {
111e7300d04SMaxime Bizon u32 tmp;
112e7300d04SMaxime Bizon
113e7300d04SMaxime Bizon tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
114e7300d04SMaxime Bizon tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
115e7300d04SMaxime Bizon bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
116e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
117e7300d04SMaxime Bizon }
118e7300d04SMaxime Bizon
119e7300d04SMaxime Bizon void __iomem *pci_iospace_start;
120e7300d04SMaxime Bizon
bcm63xx_reset_pcie(void)12119c860d9SJonas Gorski static void __init bcm63xx_reset_pcie(void)
12219c860d9SJonas Gorski {
12319c860d9SJonas Gorski u32 val;
124a156ba61SJonas Gorski u32 reg;
12519c860d9SJonas Gorski
12619c860d9SJonas Gorski /* enable SERDES */
127a156ba61SJonas Gorski if (BCMCPU_IS_6328())
128a156ba61SJonas Gorski reg = MISC_SERDES_CTRL_6328_REG;
129a156ba61SJonas Gorski else
130a156ba61SJonas Gorski reg = MISC_SERDES_CTRL_6362_REG;
131a156ba61SJonas Gorski
132a156ba61SJonas Gorski val = bcm_misc_readl(reg);
13319c860d9SJonas Gorski val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
134a156ba61SJonas Gorski bcm_misc_writel(val, reg);
13519c860d9SJonas Gorski
13619c860d9SJonas Gorski /* reset the PCIe core */
137ba00e2e5SJonas Gorski bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
138ba00e2e5SJonas Gorski bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
13919c860d9SJonas Gorski mdelay(10);
14019c860d9SJonas Gorski
141ba00e2e5SJonas Gorski bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
14219c860d9SJonas Gorski mdelay(10);
14319c860d9SJonas Gorski
144ba00e2e5SJonas Gorski bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
14519c860d9SJonas Gorski mdelay(200);
14619c860d9SJonas Gorski }
14719c860d9SJonas Gorski
148f2d1035eSJonas Gorski static struct clk *pcie_clk;
149f2d1035eSJonas Gorski
bcm63xx_register_pcie(void)15019c860d9SJonas Gorski static int __init bcm63xx_register_pcie(void)
15119c860d9SJonas Gorski {
15219c860d9SJonas Gorski u32 val;
15319c860d9SJonas Gorski
154f2d1035eSJonas Gorski /* enable clock */
155f2d1035eSJonas Gorski pcie_clk = clk_get(NULL, "pcie");
156f2d1035eSJonas Gorski if (IS_ERR_OR_NULL(pcie_clk))
157f2d1035eSJonas Gorski return -ENODEV;
158f2d1035eSJonas Gorski
159f2d1035eSJonas Gorski clk_prepare_enable(pcie_clk);
160f2d1035eSJonas Gorski
16119c860d9SJonas Gorski bcm63xx_reset_pcie();
16219c860d9SJonas Gorski
16319c860d9SJonas Gorski /* configure the PCIe bridge */
16419c860d9SJonas Gorski val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
16519c860d9SJonas Gorski val |= OPT1_RD_BE_OPT_EN;
16619c860d9SJonas Gorski val |= OPT1_RD_REPLY_BE_FIX_EN;
16719c860d9SJonas Gorski val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
16819c860d9SJonas Gorski val |= OPT1_L1_INT_STATUS_MASK_POL;
16919c860d9SJonas Gorski bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
17019c860d9SJonas Gorski
17119c860d9SJonas Gorski /* setup the interrupts */
17219c860d9SJonas Gorski val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
17319c860d9SJonas Gorski val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
17419c860d9SJonas Gorski bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
17519c860d9SJonas Gorski
17619c860d9SJonas Gorski val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
17719c860d9SJonas Gorski /* enable credit checking and error checking */
17819c860d9SJonas Gorski val |= OPT2_TX_CREDIT_CHK_EN;
17919c860d9SJonas Gorski val |= OPT2_UBUS_UR_DECODE_DIS;
18019c860d9SJonas Gorski
18119c860d9SJonas Gorski /* set device bus/func for the pcie device */
18219c860d9SJonas Gorski val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
18319c860d9SJonas Gorski val |= OPT2_CFG_TYPE1_BD_SEL;
18419c860d9SJonas Gorski bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
18519c860d9SJonas Gorski
18619c860d9SJonas Gorski /* setup class code as bridge */
18719c860d9SJonas Gorski val = bcm_pcie_readl(PCIE_IDVAL3_REG);
18819c860d9SJonas Gorski val &= ~IDVAL3_CLASS_CODE_MASK;
189*904b10fbSPali Rohár val |= PCI_CLASS_BRIDGE_PCI_NORMAL;
19019c860d9SJonas Gorski bcm_pcie_writel(val, PCIE_IDVAL3_REG);
19119c860d9SJonas Gorski
19219c860d9SJonas Gorski /* disable bar1 size */
19319c860d9SJonas Gorski val = bcm_pcie_readl(PCIE_CONFIG2_REG);
19419c860d9SJonas Gorski val &= ~CONFIG2_BAR1_SIZE_MASK;
19519c860d9SJonas Gorski bcm_pcie_writel(val, PCIE_CONFIG2_REG);
19619c860d9SJonas Gorski
19719c860d9SJonas Gorski /* set bar0 to little endian */
19819c860d9SJonas Gorski val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
19919c860d9SJonas Gorski val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
20019c860d9SJonas Gorski val |= BASEMASK_REMAP_EN;
20119c860d9SJonas Gorski bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
20219c860d9SJonas Gorski
20319c860d9SJonas Gorski val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
20419c860d9SJonas Gorski bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
20519c860d9SJonas Gorski
20619c860d9SJonas Gorski register_pci_controller(&bcm63xx_pcie_controller);
20719c860d9SJonas Gorski
20819c860d9SJonas Gorski return 0;
20919c860d9SJonas Gorski }
21019c860d9SJonas Gorski
bcm63xx_register_pci(void)21176f42fe8SJonas Gorski static int __init bcm63xx_register_pci(void)
212e7300d04SMaxime Bizon {
213e7300d04SMaxime Bizon unsigned int mem_size;
214e7300d04SMaxime Bizon u32 val;
215e7300d04SMaxime Bizon /*
216e7300d04SMaxime Bizon * configuration access are done through IO space, remap 4
217e7300d04SMaxime Bizon * first bytes to access it from CPU.
218e7300d04SMaxime Bizon *
219e7300d04SMaxime Bizon * this means that no io access from CPU should happen while
220e7300d04SMaxime Bizon * we do a configuration cycle, but there's no way we can add
221e7300d04SMaxime Bizon * a spinlock for each io access, so this is currently kind of
222e7300d04SMaxime Bizon * broken on SMP.
223e7300d04SMaxime Bizon */
2244bdc0d67SChristoph Hellwig pci_iospace_start = ioremap(BCM_PCI_IO_BASE_PA, 4);
225e7300d04SMaxime Bizon if (!pci_iospace_start)
226e7300d04SMaxime Bizon return -ENOMEM;
227e7300d04SMaxime Bizon
228e7300d04SMaxime Bizon /* setup local bus to PCI access (PCI memory) */
229e7300d04SMaxime Bizon val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
230e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
231e7300d04SMaxime Bizon bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
232e7300d04SMaxime Bizon bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
233e7300d04SMaxime Bizon
234e7300d04SMaxime Bizon /* set Cardbus IDSEL (type 0 cfg access on primary bus for
235e7300d04SMaxime Bizon * this IDSEL will be done on Cardbus instead) */
236e7300d04SMaxime Bizon val = bcm_pcmcia_readl(PCMCIA_C1_REG);
237e7300d04SMaxime Bizon val &= ~PCMCIA_C1_CBIDSEL_MASK;
238e7300d04SMaxime Bizon val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
239e7300d04SMaxime Bizon bcm_pcmcia_writel(val, PCMCIA_C1_REG);
240e7300d04SMaxime Bizon
241e7300d04SMaxime Bizon #ifdef CONFIG_CARDBUS
242e7300d04SMaxime Bizon /* setup local bus to PCI access (Cardbus memory) */
243e7300d04SMaxime Bizon val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
244e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
245e7300d04SMaxime Bizon bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
246e7300d04SMaxime Bizon val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
247e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
248e7300d04SMaxime Bizon #else
249e7300d04SMaxime Bizon /* disable second access windows */
250e7300d04SMaxime Bizon bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
251e7300d04SMaxime Bizon #endif
252e7300d04SMaxime Bizon
253e7300d04SMaxime Bizon /* setup local bus to PCI access (IO memory), we have only 1
254e7300d04SMaxime Bizon * IO window for both PCI and cardbus, but it cannot handle
255e7300d04SMaxime Bizon * both at the same time, assume standard PCI for now, if
256e7300d04SMaxime Bizon * cardbus card has IO zone, PCI fixup will change window to
257e7300d04SMaxime Bizon * cardbus */
258e7300d04SMaxime Bizon val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
259e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
260e7300d04SMaxime Bizon bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
261e7300d04SMaxime Bizon bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
262e7300d04SMaxime Bizon
263e7300d04SMaxime Bizon /* enable PCI related GPIO pins */
264e7300d04SMaxime Bizon bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
265e7300d04SMaxime Bizon
266e7300d04SMaxime Bizon /* setup PCI to local bus access, used by PCI device to target
267e7300d04SMaxime Bizon * local RAM while bus mastering */
268e7300d04SMaxime Bizon bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
2697b933421SFlorian Fainelli if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
270e7300d04SMaxime Bizon val = MPI_SP0_REMAP_ENABLE_MASK;
271e7300d04SMaxime Bizon else
272e7300d04SMaxime Bizon val = 0;
273e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
274e7300d04SMaxime Bizon
275e7300d04SMaxime Bizon bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
276e7300d04SMaxime Bizon bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
277e7300d04SMaxime Bizon
278e7300d04SMaxime Bizon mem_size = bcm63xx_get_memory_size();
279e7300d04SMaxime Bizon
280e7300d04SMaxime Bizon /* 6348 before rev b0 exposes only 16 MB of RAM memory through
281e7300d04SMaxime Bizon * PCI, throw a warning if we have more memory */
282e7300d04SMaxime Bizon if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
283e7300d04SMaxime Bizon if (mem_size > (16 * 1024 * 1024))
284e7300d04SMaxime Bizon printk(KERN_WARNING "bcm63xx: this CPU "
285e7300d04SMaxime Bizon "revision cannot handle more than 16MB "
286e7300d04SMaxime Bizon "of RAM for PCI bus mastering\n");
287e7300d04SMaxime Bizon } else {
288e7300d04SMaxime Bizon /* setup sp0 range to local RAM size */
289e7300d04SMaxime Bizon bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
290e7300d04SMaxime Bizon bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
291e7300d04SMaxime Bizon }
292e7300d04SMaxime Bizon
293e7300d04SMaxime Bizon /* change host bridge retry counter to infinite number of
294e7300d04SMaxime Bizon * retry, needed for some broadcom wifi cards with Silicon
295e7300d04SMaxime Bizon * Backplane bus where access to srom seems very slow */
296e7300d04SMaxime Bizon val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
297e7300d04SMaxime Bizon val &= ~REG_TIMER_RETRY_MASK;
298e7300d04SMaxime Bizon bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
299e7300d04SMaxime Bizon
300e7300d04SMaxime Bizon /* enable memory decoder and bus mastering */
301e7300d04SMaxime Bizon val = bcm63xx_int_cfg_readl(PCI_COMMAND);
302e7300d04SMaxime Bizon val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
303e7300d04SMaxime Bizon bcm63xx_int_cfg_writel(val, PCI_COMMAND);
304e7300d04SMaxime Bizon
305e7300d04SMaxime Bizon /* enable read prefetching & disable byte swapping for bus
306e7300d04SMaxime Bizon * mastering transfers */
307e7300d04SMaxime Bizon val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
308e7300d04SMaxime Bizon val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
309e7300d04SMaxime Bizon val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
310e7300d04SMaxime Bizon val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
311e7300d04SMaxime Bizon val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
312e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
313e7300d04SMaxime Bizon
314e7300d04SMaxime Bizon /* enable pci interrupt */
315e7300d04SMaxime Bizon val = bcm_mpi_readl(MPI_LOCINT_REG);
316e7300d04SMaxime Bizon val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
317e7300d04SMaxime Bizon bcm_mpi_writel(val, MPI_LOCINT_REG);
318e7300d04SMaxime Bizon
319e7300d04SMaxime Bizon register_pci_controller(&bcm63xx_controller);
320e7300d04SMaxime Bizon
321e7300d04SMaxime Bizon #ifdef CONFIG_CARDBUS
322e7300d04SMaxime Bizon register_pci_controller(&bcm63xx_cb_controller);
323e7300d04SMaxime Bizon #endif
324e7300d04SMaxime Bizon
325e7300d04SMaxime Bizon /* mark memory space used for IO mapping as reserved */
326e7300d04SMaxime Bizon request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
327e7300d04SMaxime Bizon "bcm63xx PCI IO space");
328e7300d04SMaxime Bizon return 0;
329e7300d04SMaxime Bizon }
330e7300d04SMaxime Bizon
33176f42fe8SJonas Gorski
bcm63xx_pci_init(void)33276f42fe8SJonas Gorski static int __init bcm63xx_pci_init(void)
33376f42fe8SJonas Gorski {
33476f42fe8SJonas Gorski if (!bcm63xx_pci_enabled)
33576f42fe8SJonas Gorski return -ENODEV;
33676f42fe8SJonas Gorski
33776f42fe8SJonas Gorski switch (bcm63xx_get_cpu_id()) {
33819c860d9SJonas Gorski case BCM6328_CPU_ID:
339a156ba61SJonas Gorski case BCM6362_CPU_ID:
34019c860d9SJonas Gorski return bcm63xx_register_pcie();
3417b933421SFlorian Fainelli case BCM3368_CPU_ID:
34276f42fe8SJonas Gorski case BCM6348_CPU_ID:
34376f42fe8SJonas Gorski case BCM6358_CPU_ID:
34476f42fe8SJonas Gorski case BCM6368_CPU_ID:
34576f42fe8SJonas Gorski return bcm63xx_register_pci();
34676f42fe8SJonas Gorski default:
34776f42fe8SJonas Gorski return -ENODEV;
34876f42fe8SJonas Gorski }
34976f42fe8SJonas Gorski }
35076f42fe8SJonas Gorski
351e7300d04SMaxime Bizon arch_initcall(bcm63xx_pci_init);
352