Lines Matching full:val
555 u32 val; in sds_wr() local
565 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
566 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
568 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
577 u32 val; in sds_rd() local
585 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
586 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
589 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
598 u32 val; in cmu_wr() local
607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
608 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
628 u32 val; in cmu_toggle1to0() local
630 cmu_rd(ctx, cmu_type, reg, &val); in cmu_toggle1to0()
631 val |= bits; in cmu_toggle1to0()
632 cmu_wr(ctx, cmu_type, reg, val); in cmu_toggle1to0()
633 cmu_rd(ctx, cmu_type, reg, &val); in cmu_toggle1to0()
634 val &= ~bits; in cmu_toggle1to0()
635 cmu_wr(ctx, cmu_type, reg, val); in cmu_toggle1to0()
641 u32 val; in cmu_clrbits() local
643 cmu_rd(ctx, cmu_type, reg, &val); in cmu_clrbits()
644 val &= ~bits; in cmu_clrbits()
645 cmu_wr(ctx, cmu_type, reg, val); in cmu_clrbits()
651 u32 val; in cmu_setbits() local
653 cmu_rd(ctx, cmu_type, reg, &val); in cmu_setbits()
654 val |= bits; in cmu_setbits()
655 cmu_wr(ctx, cmu_type, reg, val); in cmu_setbits()
661 u32 val; in serdes_wr() local
668 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in serdes_wr()
670 val); in serdes_wr()
687 u32 val; in serdes_clrbits() local
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 val &= ~bits; in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
697 u32 val; in serdes_setbits() local
699 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
700 val |= bits; in serdes_setbits()
701 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
708 u32 val; in xgene_phy_cfg_cmu_clk_type() local
711 cmu_rd(ctx, cmu_type, CMU_REG12, &val); in xgene_phy_cfg_cmu_clk_type()
712 val = CMU_REG12_STATE_DELAY9_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
713 cmu_wr(ctx, cmu_type, CMU_REG12, val); in xgene_phy_cfg_cmu_clk_type()
721 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_cfg_cmu_clk_type()
722 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
723 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_cfg_cmu_clk_type()
725 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
726 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
727 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
731 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_cfg_cmu_clk_type()
732 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
733 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_cfg_cmu_clk_type()
735 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
736 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
737 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
746 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
747 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); in xgene_phy_cfg_cmu_clk_type()
748 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
750 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
751 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); in xgene_phy_cfg_cmu_clk_type()
752 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
762 u32 val; in xgene_phy_sata_cfg_cmu_core() local
767 cmu_rd(ctx, cmu_type, CMU_REG34, &val); in xgene_phy_sata_cfg_cmu_core()
768 val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
769 val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc); in xgene_phy_sata_cfg_cmu_core()
770 val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
771 val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8); in xgene_phy_sata_cfg_cmu_core()
772 cmu_wr(ctx, cmu_type, CMU_REG34, val); in xgene_phy_sata_cfg_cmu_core()
776 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_sata_cfg_cmu_core()
778 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
780 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
781 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_sata_cfg_cmu_core()
784 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_sata_cfg_cmu_core()
785 val = CMU_REG1_PLL_CP_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
787 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); in xgene_phy_sata_cfg_cmu_core()
789 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
791 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
793 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
794 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_sata_cfg_cmu_core()
800 cmu_rd(ctx, cmu_type, CMU_REG2, &val); in xgene_phy_sata_cfg_cmu_core()
802 val = CMU_REG2_PLL_LFRES_SET(val, 0xa); in xgene_phy_sata_cfg_cmu_core()
805 val = CMU_REG2_PLL_LFRES_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
812 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M); in xgene_phy_sata_cfg_cmu_core()
813 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M); in xgene_phy_sata_cfg_cmu_core()
815 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M); in xgene_phy_sata_cfg_cmu_core()
816 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M); in xgene_phy_sata_cfg_cmu_core()
818 cmu_wr(ctx, cmu_type, CMU_REG2, val); in xgene_phy_sata_cfg_cmu_core()
821 cmu_rd(ctx, cmu_type, CMU_REG3, &val); in xgene_phy_sata_cfg_cmu_core()
823 val = CMU_REG3_VCOVARSEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
824 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10); in xgene_phy_sata_cfg_cmu_core()
826 val = CMU_REG3_VCOVARSEL_SET(val, 0xF); in xgene_phy_sata_cfg_cmu_core()
828 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15); in xgene_phy_sata_cfg_cmu_core()
830 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a); in xgene_phy_sata_cfg_cmu_core()
831 val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15); in xgene_phy_sata_cfg_cmu_core()
833 cmu_wr(ctx, cmu_type, CMU_REG3, val); in xgene_phy_sata_cfg_cmu_core()
836 cmu_rd(ctx, cmu_type, CMU_REG26, &val); in xgene_phy_sata_cfg_cmu_core()
837 val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
838 cmu_wr(ctx, cmu_type, CMU_REG26, val); in xgene_phy_sata_cfg_cmu_core()
841 cmu_rd(ctx, cmu_type, CMU_REG5, &val); in xgene_phy_sata_cfg_cmu_core()
842 val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
843 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
845 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
847 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
848 cmu_wr(ctx, cmu_type, CMU_REG5, val); in xgene_phy_sata_cfg_cmu_core()
851 cmu_rd(ctx, cmu_type, CMU_REG6, &val); in xgene_phy_sata_cfg_cmu_core()
852 val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2); in xgene_phy_sata_cfg_cmu_core()
853 val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0); in xgene_phy_sata_cfg_cmu_core()
854 cmu_wr(ctx, cmu_type, CMU_REG6, val); in xgene_phy_sata_cfg_cmu_core()
858 cmu_rd(ctx, cmu_type, CMU_REG9, &val); in xgene_phy_sata_cfg_cmu_core()
859 val = CMU_REG9_TX_WORD_MODE_CH1_SET(val, in xgene_phy_sata_cfg_cmu_core()
861 val = CMU_REG9_TX_WORD_MODE_CH0_SET(val, in xgene_phy_sata_cfg_cmu_core()
863 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
865 val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
866 val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0); in xgene_phy_sata_cfg_cmu_core()
868 cmu_wr(ctx, cmu_type, CMU_REG9, val); in xgene_phy_sata_cfg_cmu_core()
871 cmu_rd(ctx, cmu_type, CMU_REG10, &val); in xgene_phy_sata_cfg_cmu_core()
872 val = CMU_REG10_VREG_REFSEL_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
873 cmu_wr(ctx, cmu_type, CMU_REG10, val); in xgene_phy_sata_cfg_cmu_core()
877 cmu_rd(ctx, cmu_type, CMU_REG16, &val); in xgene_phy_sata_cfg_cmu_core()
878 val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
879 val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
881 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4); in xgene_phy_sata_cfg_cmu_core()
883 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); in xgene_phy_sata_cfg_cmu_core()
884 cmu_wr(ctx, cmu_type, CMU_REG16, val); in xgene_phy_sata_cfg_cmu_core()
887 cmu_rd(ctx, cmu_type, CMU_REG30, &val); in xgene_phy_sata_cfg_cmu_core()
888 val = CMU_REG30_PCIE_MODE_SET(val, 0x0); in xgene_phy_sata_cfg_cmu_core()
889 val = CMU_REG30_LOCK_COUNT_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
890 cmu_wr(ctx, cmu_type, CMU_REG30, val); in xgene_phy_sata_cfg_cmu_core()
895 cmu_rd(ctx, cmu_type, CMU_REG32, &val); in xgene_phy_sata_cfg_cmu_core()
896 val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
898 val = CMU_REG32_IREF_ADJ_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()
900 val = CMU_REG32_IREF_ADJ_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()
901 cmu_wr(ctx, cmu_type, CMU_REG32, val); in xgene_phy_sata_cfg_cmu_core()
916 u32 val; in xgene_phy_ssc_enable() local
919 cmu_rd(ctx, cmu_type, CMU_REG35, &val); in xgene_phy_ssc_enable()
920 val = CMU_REG35_PLL_SSC_MOD_SET(val, 98); in xgene_phy_ssc_enable()
921 cmu_wr(ctx, cmu_type, CMU_REG35, val); in xgene_phy_ssc_enable()
924 cmu_rd(ctx, cmu_type, CMU_REG36, &val); in xgene_phy_ssc_enable()
925 val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30); in xgene_phy_ssc_enable()
926 val = CMU_REG36_PLL_SSC_EN_SET(val, 1); in xgene_phy_ssc_enable()
927 val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1); in xgene_phy_ssc_enable()
928 cmu_wr(ctx, cmu_type, CMU_REG36, val); in xgene_phy_ssc_enable()
941 u32 val; in xgene_phy_sata_cfg_lanes() local
950 serdes_rd(ctx, lane, RXTX_REG0, &val); in xgene_phy_sata_cfg_lanes()
951 val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
952 val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
953 val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
954 serdes_wr(ctx, lane, RXTX_REG0, val); in xgene_phy_sata_cfg_lanes()
957 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
958 val = RXTX_REG1_RXACVCM_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
959 val = RXTX_REG1_CTLE_EQ_SET(val, in xgene_phy_sata_cfg_lanes()
962 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
967 serdes_rd(ctx, lane, RXTX_REG2, &val); in xgene_phy_sata_cfg_lanes()
968 val = RXTX_REG2_VTT_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
969 val = RXTX_REG2_VTT_SEL_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
970 val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
971 serdes_wr(ctx, lane, RXTX_REG2, val); in xgene_phy_sata_cfg_lanes()
974 serdes_rd(ctx, lane, RXTX_REG4, &val); in xgene_phy_sata_cfg_lanes()
975 val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); in xgene_phy_sata_cfg_lanes()
976 serdes_wr(ctx, lane, RXTX_REG4, val); in xgene_phy_sata_cfg_lanes()
979 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
980 val = RXTX_REG1_RXVREG1_SET(val, 0x2); in xgene_phy_sata_cfg_lanes()
981 val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2); in xgene_phy_sata_cfg_lanes()
982 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
986 serdes_rd(ctx, lane, RXTX_REG5, &val); in xgene_phy_sata_cfg_lanes()
987 val = RXTX_REG5_TX_CN1_SET(val, in xgene_phy_sata_cfg_lanes()
990 val = RXTX_REG5_TX_CP1_SET(val, in xgene_phy_sata_cfg_lanes()
993 val = RXTX_REG5_TX_CN2_SET(val, in xgene_phy_sata_cfg_lanes()
996 serdes_wr(ctx, lane, RXTX_REG5, val); in xgene_phy_sata_cfg_lanes()
999 serdes_rd(ctx, lane, RXTX_REG6, &val); in xgene_phy_sata_cfg_lanes()
1000 val = RXTX_REG6_TXAMP_CNTL_SET(val, in xgene_phy_sata_cfg_lanes()
1003 val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1004 val = RXTX_REG6_TX_IDLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1005 val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1006 val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1007 serdes_wr(ctx, lane, RXTX_REG6, val); in xgene_phy_sata_cfg_lanes()
1010 serdes_rd(ctx, lane, RXTX_REG7, &val); in xgene_phy_sata_cfg_lanes()
1011 val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1012 val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); in xgene_phy_sata_cfg_lanes()
1013 serdes_wr(ctx, lane, RXTX_REG7, val); in xgene_phy_sata_cfg_lanes()
1016 serdes_rd(ctx, lane, RXTX_REG8, &val); in xgene_phy_sata_cfg_lanes()
1017 val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1018 val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1019 val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1020 val = RXTX_REG8_SD_DISABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1021 val = RXTX_REG8_SD_VREF_SET(val, 0x4); in xgene_phy_sata_cfg_lanes()
1022 serdes_wr(ctx, lane, RXTX_REG8, val); in xgene_phy_sata_cfg_lanes()
1025 serdes_rd(ctx, lane, RXTX_REG11, &val); in xgene_phy_sata_cfg_lanes()
1026 val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1027 serdes_wr(ctx, lane, RXTX_REG11, val); in xgene_phy_sata_cfg_lanes()
1030 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_sata_cfg_lanes()
1031 val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1032 val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1033 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1034 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_sata_cfg_lanes()
1037 serdes_rd(ctx, lane, RXTX_REG26, &val); in xgene_phy_sata_cfg_lanes()
1038 val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1039 val = RXTX_REG26_BLWC_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1040 serdes_wr(ctx, lane, RXTX_REG26, val); in xgene_phy_sata_cfg_lanes()
1048 serdes_rd(ctx, lane, RXTX_REG61, &val); in xgene_phy_sata_cfg_lanes()
1049 val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1050 val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1051 val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1052 serdes_wr(ctx, lane, RXTX_REG61, val); in xgene_phy_sata_cfg_lanes()
1054 serdes_rd(ctx, lane, RXTX_REG62, &val); in xgene_phy_sata_cfg_lanes()
1055 val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1056 serdes_wr(ctx, lane, RXTX_REG62, val); in xgene_phy_sata_cfg_lanes()
1061 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1062 val = RXTX_REG89_MU_TH7_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1063 val = RXTX_REG89_MU_TH8_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1064 val = RXTX_REG89_MU_TH9_SET(val, 0xe); in xgene_phy_sata_cfg_lanes()
1065 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1071 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1072 val = RXTX_REG96_MU_FREQ1_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1073 val = RXTX_REG96_MU_FREQ2_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1074 val = RXTX_REG96_MU_FREQ3_SET(val, 0x10); in xgene_phy_sata_cfg_lanes()
1075 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1081 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1082 val = RXTX_REG99_MU_PHASE1_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1083 val = RXTX_REG99_MU_PHASE2_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1084 val = RXTX_REG99_MU_PHASE3_SET(val, 0x7); in xgene_phy_sata_cfg_lanes()
1085 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1088 serdes_rd(ctx, lane, RXTX_REG102, &val); in xgene_phy_sata_cfg_lanes()
1089 val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1090 serdes_wr(ctx, lane, RXTX_REG102, val); in xgene_phy_sata_cfg_lanes()
1094 serdes_rd(ctx, lane, RXTX_REG125, &val); in xgene_phy_sata_cfg_lanes()
1095 val = RXTX_REG125_SIGN_PQ_SET(val, in xgene_phy_sata_cfg_lanes()
1098 val = RXTX_REG125_PQ_REG_SET(val, in xgene_phy_sata_cfg_lanes()
1101 val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1102 serdes_wr(ctx, lane, RXTX_REG125, val); in xgene_phy_sata_cfg_lanes()
1104 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1105 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1106 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1108 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_sata_cfg_lanes()
1109 val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_lanes()
1110 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_sata_cfg_lanes()
1112 serdes_rd(ctx, lane, RXTX_REG145, &val); in xgene_phy_sata_cfg_lanes()
1113 val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3); in xgene_phy_sata_cfg_lanes()
1114 val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1116 val = RXTX_REG145_RXES_ENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1117 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1); in xgene_phy_sata_cfg_lanes()
1119 val = RXTX_REG145_RXES_ENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1120 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0); in xgene_phy_sata_cfg_lanes()
1122 serdes_wr(ctx, lane, RXTX_REG145, val); in xgene_phy_sata_cfg_lanes()
1141 u32 val; in xgene_phy_cal_rdy_chk() local
1155 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cal_rdy_chk()
1156 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1157 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cal_rdy_chk()
1181 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1182 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12); in xgene_phy_cal_rdy_chk()
1183 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1184 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1192 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1193 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29); in xgene_phy_cal_rdy_chk()
1194 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1195 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1199 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1200 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28); in xgene_phy_cal_rdy_chk()
1201 val = CMU_REG17_RESERVED_7_SET(val, 0x0); in xgene_phy_cal_rdy_chk()
1202 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1210 cmu_rd(ctx, cmu_type, CMU_REG7, &val); in xgene_phy_cal_rdy_chk()
1211 if (CMU_REG7_PLL_CALIB_DONE_RD(val)) in xgene_phy_cal_rdy_chk()
1220 cmu_rd(ctx, cmu_type, CMU_REG7, &val); in xgene_phy_cal_rdy_chk()
1222 CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed"); in xgene_phy_cal_rdy_chk()
1223 if (CMU_REG7_VCO_CAL_FAIL_RD(val)) { in xgene_phy_cal_rdy_chk()
1230 cmu_rd(ctx, cmu_type, CMU_REG15, &val); in xgene_phy_cal_rdy_chk()
1231 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1239 u32 val; in xgene_phy_pdwn_force_vco() local
1243 cmu_rd(ctx, cmu_type, CMU_REG16, &val); in xgene_phy_pdwn_force_vco()
1244 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); in xgene_phy_pdwn_force_vco()
1245 cmu_wr(ctx, cmu_type, CMU_REG16, val); in xgene_phy_pdwn_force_vco()
1257 u32 val; in xgene_phy_hw_init_sata() local
1264 val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ in xgene_phy_hw_init_sata()
1273 val = readl(sds_base + SATA_ENET_SDS_CTL1); in xgene_phy_hw_init_sata()
1274 val = CFG_I_SPD_SEL_CDR_OVR1_SET(val, in xgene_phy_hw_init_sata()
1276 writel(val, sds_base + SATA_ENET_SDS_CTL1); in xgene_phy_hw_init_sata()
1279 val = readl(sds_base + SATA_ENET_SDS_CTL0); in xgene_phy_hw_init_sata()
1280 val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421); in xgene_phy_hw_init_sata()
1281 writel(val, sds_base + SATA_ENET_SDS_CTL0); in xgene_phy_hw_init_sata()
1297 val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0); in xgene_phy_hw_init_sata()
1298 val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3); in xgene_phy_hw_init_sata()
1299 val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3); in xgene_phy_hw_init_sata()
1300 writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0); in xgene_phy_hw_init_sata()
1349 u32 val; in xgene_phy_force_lat_summer_cal() member
1407 serdes_reg[i].val); in xgene_phy_force_lat_summer_cal()
1436 u32 val; in xgene_phy_gen_avg_val() local
1460 serdes_rd(ctx, lane, RXTX_REG21, &val); in xgene_phy_gen_avg_val()
1461 lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1462 lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1463 fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val); in xgene_phy_gen_avg_val()
1465 serdes_rd(ctx, lane, RXTX_REG22, &val); in xgene_phy_gen_avg_val()
1466 lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1467 lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1468 fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val); in xgene_phy_gen_avg_val()
1470 serdes_rd(ctx, lane, RXTX_REG23, &val); in xgene_phy_gen_avg_val()
1471 lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1472 lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1474 serdes_rd(ctx, lane, RXTX_REG24, &val); in xgene_phy_gen_avg_val()
1475 lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1476 lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val); in xgene_phy_gen_avg_val()
1478 serdes_rd(ctx, lane, RXTX_REG121, &val); in xgene_phy_gen_avg_val()
1479 sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val); in xgene_phy_gen_avg_val()
1512 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1513 val = RXTX_REG127_DO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1515 val = RXTX_REG127_XO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1517 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1519 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_gen_avg_val()
1520 val = RXTX_REG128_EO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1522 val = RXTX_REG128_SO_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1524 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_gen_avg_val()
1526 serdes_rd(ctx, lane, RXTX_REG129, &val); in xgene_phy_gen_avg_val()
1527 val = RXTX_REG129_DE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1529 val = RXTX_REG129_XE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1531 serdes_wr(ctx, lane, RXTX_REG129, val); in xgene_phy_gen_avg_val()
1533 serdes_rd(ctx, lane, RXTX_REG130, &val); in xgene_phy_gen_avg_val()
1534 val = RXTX_REG130_EE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1536 val = RXTX_REG130_SE_LATCH_MANCAL_SET(val, in xgene_phy_gen_avg_val()
1538 serdes_wr(ctx, lane, RXTX_REG130, val); in xgene_phy_gen_avg_val()
1541 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1542 val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val, in xgene_phy_gen_avg_val()
1544 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1560 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1561 val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1); in xgene_phy_gen_avg_val()
1562 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1565 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1566 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1); in xgene_phy_gen_avg_val()
1568 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1571 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_gen_avg_val()
1572 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0); in xgene_phy_gen_avg_val()
1573 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_gen_avg_val()