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/linux/sound/soc/sprd/
H A Dsprd-pcm-compress.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/dma-mapping.h>
6 #include <linux/dma/sprd-dma.h>
14 #include "sprd-pcm-dma.h"
28 /* Stage 0 IRAM buffer size definition */
31 #define SPRD_COMPR_IRAM_LINKLIST_SIZE (1024 - SPRD_COMPR_IRAM_INFO_SIZE)
52 * The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to
58 * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
59 * power-on) and DDR buffer. The source channel will transfer data from IRAM
60 * buffer to the DSP fifo to decoding/encoding, once IRAM buffer is empty by
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/linux/Documentation/devicetree/bindings/net/
H A Dnxp,lpc-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,lpc-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
14 const: nxp,lpc-eth
25 use-iram:
27 description: Use LPC32xx internal SRAM (IRAM) for DMA buffering
30 - compatible
31 - reg
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/linux/drivers/net/phy/aquantia/
H A Daquantia_firmware.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/crc-itu-t.h>
7 #include <linux/nvmem-consumer.h>
47 /* AQR firmware doesn't have fixed offsets for iram and dram section
48 * but instead provide an header with the offset to use on reading
62 return -EINVAL; in aqr_fw_get_be16()
72 return -EINVAL; in aqr_fw_get_le16()
82 return -EINVAL; in aqr_fw_get_le24()
113 /* FW data is always stored in little-endian */ in aqr_fw_load_memory()
126 * using big-endian order. Mimic what the PHY does to have a in aqr_fw_load_memory()
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 Each Programmable Real-Time Unit and Industrial Communication Subsystem
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
17 use the Data RAMs present within the PRU-ICSS for code execution.
27 corresponding PRU-ICSS node. Each node can optionally be rendered inactive by
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H A Dti,k3-m4f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hari Nagalla <hnagalla@ti.com>
11 - Mathieu Poirier <mathieu.poirier@linaro.org>
15 family with a M4F core. Typically safety oriented applications may use
17 home automation applications, may use the M4F core as a remote processor
20 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
25 - ti,am64-m4fss
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 (dmcu_dce->regs->reg)
42 dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
45 dmcu_dce->base.ctx
86 /* Enable write access to IRAM */ in dce_dmcu_load_iram()
98 /* Disable write access to IRAM to allow dynamic sleep state */ in dce_dmcu_load_iram()
112 /* Enable write access to IRAM */ in dce_get_dmcu_psr_state()
123 /* Disable write access to IRAM after finished using IRAM in dce_get_dmcu_psr_state()
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/linux/sound/soc/intel/atom/sst/
H A Dsst.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sst.c - Intel SST Driver for audio engine
5 * Copyright (C) 2008-14 Intel Corp
28 #include "../sst-mfld-platform.h"
57 isr.full = sst_shim_read64(drv->shim, SST_ISRX); in intel_sst_interrupt_mrfld()
61 spin_lock(&drv->ipc_spin_lock); in intel_sst_interrupt_mrfld()
62 header.full = sst_shim_read64(drv->shim, in intel_sst_interrupt_mrfld()
63 drv->ipc_reg.ipcx); in intel_sst_interrupt_mrfld()
65 sst_shim_write64(drv->shim, drv->ipc_reg.ipcx, header.full); in intel_sst_interrupt_mrfld()
69 sst_shim_write64(drv->shim, SST_ISRX, isr.full); in intel_sst_interrupt_mrfld()
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H A Dsst_acpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.
23 #include <sound/intel-dsp-config.h>
31 #include <sound/soc-acpi.h>
32 #include <sound/soc-acpi-intel-match.h>
33 #include "../sst-mfld-platform.h"
34 #include "../../common/soc-intel-quirks.h"
155 .platform = "sst-mfld-platform",
167 .platform = "sst-mfld-platform",
173 struct platform_device *pdev = to_platform_device(ctx->dev); in sst_platform_get_resources()
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/linux/arch/arm/mach-tegra/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
92 * saves pll state for use by restart_plls, prepares flow controller for
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
143 return -EBUSY; in tegra_sleep_cpu()
148 * MMU-on if cache maintenance is done via Trusted Foundations in tegra_sleep_cpu()
150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
151 * code-path only for Tegra20/30. in tegra_sleep_cpu()
162 * 2) Disable D-cache. This need to be taken into account in in tegra_sleep_cpu()
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H A Dsleep-tegra30.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
81 .arch armv7-a
192 * Puts the current CPU in wait-for-event mode on the flow controller
193 * and powergates it -- flags (in R0) indicate the request type.
196 * corrupts r0-r4, r10-r12
282 * tegra30_tear_down_core in IRAM
293 * CPU power-gating process, to avoid loading from SDRAM which
294 * are not supported once SDRAM is put into self-refresh.
295 * LP0 / LP1 use physical address, since the MMU needs to be
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H A Dirammap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 /* The first 1K of IRAM is permanently reserved for the CPU reset handler */
17 * active. At other times, the AVP may use this area for arbitrary purposes
/linux/drivers/remoteproc/
H A Dpru_rproc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PRU-ICSS remoteproc driver for various TI SoCs
5 * Copyright (C) 2014-2022 Texas Instruments Incorporated - https://www.ti.com/
8 * Suman Anna <s-anna@ti.com>
11 * Puranjay Mohan <p-mohan@ti.com>
41 /* CTRL register bit-fields */
53 /* PRU/RTU/Tx_PRU Core IRAM address masks */
71 * enum pru_iomem - PRU core memory/register range identifiers
86 * struct pru_private_data - device data for a PRU core
96 * struct pru_rproc - PRU remoteproc structure
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/linux/Documentation/arch/powerpc/
H A Dqe_firmware.rst10 I - Software License for Firmware
12 II - Microcode Availability
14 III - Description and Terminology
16 IV - Microcode Programming Details
18 V - Firmware Structure Layout
20 VI - Sample Code for Creating Firmware Files
25 November 30, 2007: Rev 1.0 - Initial version
27 I - Software License for Firmware
34 II - Microcode Availability
41 III - Description and Terminology
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/linux/drivers/soc/fsl/qe/
H A Dqe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
50 static phys_addr_t qebase = -1;
72 if (qebase != -1) in get_qe_base()
97 /* Reclaim the MURAM memory for our use. */ in qe_reset()
113 iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr); in qe_issue_cmd()
116 /* Here device is the SNUM, not sub-block */ in qe_issue_cmd()
130 iowrite32be(cmd_input, &qe_immr->cp.cecdr); in qe_issue_cmd()
132 &qe_immr->cp.cecr); in qe_issue_cmd()
136 ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val, in qe_issue_cmd()
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/linux/arch/xtensa/lib/
H A Dmemcopy.S2 * arch/xtensa/lib/hal/memcopy.S -- Core HAL library functions
9 * Copyright (C) 2002 - 2012 Tensilica Inc.
24 * 32-bit load and store instructions (as required for these
28 * !!!!!!! Handling of IRAM/IROM has not yet
38 * do the same, but use SRC to align the source data.
39 * This code tries to use fall-through branches for the common
43 * Register use:
95 addi a4, a4, -1
100 .Ldst2mod4: # dst 16-bit aligned
106 addi a4, a4, -2
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/linux/drivers/soc/ti/
H A Dknav_qmss_queue.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
44 * are to be re-defined
57 (kdev->instances + (idx << kdev->inst_shift))
60 list_for_each_entry_rcu(qh, &inst->handles, list, \
64 for (idx = 0, inst = kdev->instances; \
65 idx < (kdev)->num_queues_in_use; \
84 * @inst: - qmss queue instance like accumulator
95 if (atomic_read(&qh->notifier_enabled) <= 0) in knav_queue_notify()
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/linux/sound/soc/intel/catpt/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
91 struct resource iram; member
129 * HOST <-> DSP communication yet failure to process specific request.
130 * Use below macro to convert returned non-zero values appropriately
132 #define CATPT_IPC_ERROR(err) (((err) < 0) ? (err) : -EREMOTEIO)
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda-bit.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Coda multi-standard codec IP - BIT processor functions
6 * Javier Martin, <javier.martin@vista-silicon.com>
8 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
21 #include <media/v4l2-common.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-fh.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-v4l2.h>
26 #include <media/videobuf2-dma-contig.h>
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/linux/arch/arm/mach-imx/
H A Dhardware.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
17 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
20 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
28 * - same mapping on all i.MX machines
29 * - works for assembler, too
30 * - no need to nurture #defines for virtual addresses
36 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
41 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
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H A Dsuspend-imx6.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-offsets.h>
9 #include <asm/hardware/cache-l2x0.h>
12 .arch armv7-a
17 * Better to follow below rules to use ARM registers:
38 * which defined in arch/arm/mach-imx/pm-imx6q.c, this
135 /* let DDR out of self-refresh */
158 * counting the resume address in iram
179 /* use r11 to store the IO address */
190 * put DDR explicitly into self-refresh and
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/linux/sound/soc/intel/atom/
H A Dsst-mfld-dsp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * sst_mfld_dsp.h - Intel SST Driver for audio engine
7 * Copyright (C) 2008-14 Intel Corporation
31 /* Bits B7: SST or IA/SC ; B6-B4: Msg Category; B3-B0: Msg Type */
120 /* Buffer under-run */
126 * - IPC High: pvt_id is set to zero. Always short message.
127 * - msg_id is in lower 16-bits of IPC low payload.
128 * - pipe_id is in higher 16-bits of IPC low payload for period_elapsed.
129 * - error id is in higher 16-bits of IPC low payload for async errors.
191 u32 msg_id:8; /* Message ID - Max 256 Message Types */
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/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc3250-phy3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PHYTEC phyCORE-LPC3250 board
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 /dts-v1/;
13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
22 compatible = "gpio-leds";
26 default-state = "off";
31 linux,default-trigger = "heartbeat";
37 power-supply = <&reg_lcd>;
41 remote-endpoint = <&cldc_output>;
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H A Dlpc3250-ea3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
20 gpio-keys {
21 compatible = "gpio-keys";
86 compatible = "gpio-leds";
92 linux,default-trigger = "timer";
93 default-state = "off";
98 default-state = "off";
103 default-state = "off";
108 default-state = "off";
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
12 * of limited use without interrupts, and likely reserved by the ESM.
15 compatible = "ti,am654-timer";
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
25 compatible = "ti,am654-timer";
28 clock-names = "fck";
29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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H A Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
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