Lines Matching +full:use +full:- +full:iram

1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
81 .arch armv7-a
192  * Puts the current CPU in wait-for-event mode on the flow controller
193  * and powergates it -- flags (in R0) indicate the request type.
196  * corrupts r0-r4, r10-r12
282  * tegra30_tear_down_core in IRAM
293 	 * CPU power-gating process, to avoid loading from SDRAM which
294 	 * are not supported once SDRAM is put into self-refresh.
295 	 * LP0 / LP1 use physical address, since the MMU needs to be
296 	 * disabled before putting SDRAM into self-refresh to avoid
346 /* START OF ROUTINES COPIED TO IRAM */
354  * reset vector for LP1 restore; copied into IRAM during suspend.
356  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
367 	 * IRAM when this code is executed; immediately switch to CLKM and
421 	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
529 	/* Issue a ZQ_CAL for dev0 - DDR3 */
539 	/* Issue a ZQ_CAL for dev1 - DDR3 */
548 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
558 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
630 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
633 	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
637 	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
647  * copied into and executed from IRAM
648  * puts memory in self-refresh for LP0 and LP1
692 	/* store enable-state of PLLs */
745  * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
783  * must be executed from IRAM
864 	bne	emcself			@ loop until DDR in self-refresh
904 /* dummy symbol for end of IRAM */