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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-ucc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
26 - description: Dual port ram base
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H A Dfsl,ucc-hdlc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-Level Data Link Control(HDLC)
9 description: HDLC part in Universal communication controllers (UCCs)
12 - Frank Li <Frank.Li@nxp.com>
16 const: fsl,ucc-hdlc
24 cell-index:
27 rx-clock-name:
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/linux/include/soc/fsl/qe/
H A Ducc_fast.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Internal header file for UCC FAST unit routines.
18 #include <soc/fsl/qe/ucc.h>
54 #define T_UN_S 0x0002 /* hdlc underrun */
55 #define T_CT_S 0x0001 /* hdlc carrier lost */
66 /* ucc_fast_channel_protocol_mode - UCC FAST mode */
86 /* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
92 /* UCC fast diagnostic mode */
100 /* UCC fast Sync length (transparent mode only) */
108 /* UCC fast RTS mode */
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H A Ducc_slow.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Internal header file for UCC SLOW unit routines.
19 #include <soc/fsl/qe/ucc.h>
28 #define T_A 0x04000000 /* Address - the data transmitted as address
33 #define T_P 0x01000000 /* Preamble - send Preamble sequence before
80 /* UCC Slow Channel Protocol Mode */
87 /* UCC Slow Transparent Transmit CRC (TCRC) */
89 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
93 /* 32-bit CCITT CRC (Ethernet and HDLC) */
97 /* UCC Slow oversampling rate for transmitter (TDCR) */
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H A Dqe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
112 return -ENOSYS; in cpm_muram_alloc()
118 return -ENOSYS; in devm_cpm_muram_alloc()
128 return -ENOSYS; in cpm_muram_alloc_fixed()
135 return -ENOSYS; in devm_cpm_muram_alloc_fixed()
145 return -ENOSYS; in cpm_muram_offset()
184 static inline int par_io_init(struct device_node *np) { return -ENOSYS; } in par_io_init()
185 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } in par_io_of_config()
187 int assignment, int has_irq) { return -ENOSYS; } in par_io_config_pin()
188 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } in par_io_data_set()
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/linux/drivers/net/wan/
H A Dfsl_ucc_hdlc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Freescale QUICC Engine HDLC Device Driver
16 #include <soc/fsl/qe/ucc.h>
19 /* UCC HDLC event register */
72 struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
129 #define TX_RING_MOD_MASK(size) (size - 1)
130 #define RX_RING_MOD_MASK(size) (size - 1)
/linux/drivers/soc/fsl/qe/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 This option provides qe_lib support to UCC slow
29 This option provides qe_lib support to UCC fast
30 protocols: HDLC, Ethernet, ATM, transparent
32 config UCC config
H A Dqmc.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
14 #include <linux/hdlc.h>
55 /* UCC Extended Mode Register (8 bits, QE only) */
64 /* Tx time-slot assignment table pointer (16 bits) */
76 /* Rx time-slot assignment table pointer (16 bits) */
92 /* A reserved area (0xB0 -> 0xC3) that must be initialized to 0 (QE only) */
129 /* Zero-insertion state (32 bits) */
135 /* HDLC: Maximum frame length register (16 bits) */
247 u32 zdstate_hdlc; /* Initial ZDSTATE value (HDLC mode) */
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/linux/arch/powerpc/boot/dts/fsl/
H A Dkmcent2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
11 /include/ "t104xsi-pre.dtsi"
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
26 bman_fbpr: bman-fbpr {
30 qman_fqd: qman-fqd {
34 qman_pfdr: qman-pfdr {
50 #address-cells = <1>;
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H A Dt104xrdb.dtsi4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
47 bman_fbpr: bman-fbpr {
51 qman_fqd: qman-fqd {
55 qman_pfdr: qman-pfdr {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flash";
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H A Dt104xd4rdb.dtsi36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
66 bank-width = <2>;
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H A Dt104xqds.dtsi4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
37 #address-cells = <2>;
38 #size-cells = <2>;
39 interrupt-parent = <&mpic>;
68 reserved-memory {
69 #address-cells = <2>;
70 #size-cells = <2>;
73 bman_fbpr: bman-fbpr {
77 qman_fqd: qman-fqd {
81 qman_pfdr: qman-pfdr {
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
36 shunt-resistor = <1000>;
67 #address-cells = <2>;
68 #size-cells = <1>;
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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