Lines Matching +full:ucc +full:- +full:hdlc

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 		stdout-path = "serial0:115200n8";
36 		shunt-resistor = <1000>;
67 	#address-cells = <2>;
68 	#size-cells = <1>;
75 			compatible = "cfi-flash";
76 			#address-cells = <1>;
77 			#size-cells = <1>;
79 			big-endian;
80 			bank-width = <2>;
81 			device-width = <1>;
85 			compatible = "fsl,ifc-nand";
86 			#address-cells = <1>;
87 			#size-cells = <1>;
91 		cpld: board-control@2,0 {
92 			compatible = "fsl,ls1043ardb-cpld";
98 	bus-num = <0>;
102 		#address-cells = <1>;
103 		#size-cells = <1>;
104 		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
106 		spi-max-frequency = <1000000>; /* input clock */
111 		spi-cs-setup-delay-ns = <100>;
112 		spi-cs-hold-delay-ns = <100>;
113 		fsl,spi-cs-sck-delay = <100>;
114 		fsl,spi-sck-cs-delay = <100>;
120 		spi-max-frequency = <2000000>;
125 		spi-cs-setup-delay-ns = <100>;
126 		spi-cs-hold-delay-ns = <50>;
127 		fsl,spi-cs-sck-delay = <100>;
128 		fsl,spi-sck-cs-delay = <50>;
134 		spi-max-frequency = <2000000>;
139 		spi-cs-setup-delay-ns = <100>;
140 		spi-cs-hold-delay-ns = <50>;
141 		fsl,spi-cs-sck-delay = <100>;
142 		fsl,spi-sck-cs-delay = <50>;
154 #include "fsl-ls1043-post.dtsi"
158 		phy-handle = <&qsgmii_phy1>;
159 		phy-connection-type = "qsgmii";
163 		phy-handle = <&qsgmii_phy2>;
164 		phy-connection-type = "qsgmii";
168 		phy-handle = <&rgmii_phy1>;
169 		phy-connection-type = "rgmii-id";
173 		phy-handle = <&rgmii_phy2>;
174 		phy-connection-type = "rgmii-id";
178 		phy-handle = <&qsgmii_phy3>;
179 		phy-connection-type = "qsgmii";
183 		phy-handle = <&qsgmii_phy4>;
184 		phy-connection-type = "qsgmii";
188 		phy-handle = <&aqr105_phy>;
189 		phy-connection-type = "xgmii";
193 		rgmii_phy1: ethernet-phy@1 {
197 		rgmii_phy2: ethernet-phy@2 {
201 		qsgmii_phy1: ethernet-phy@4 {
205 		qsgmii_phy2: ethernet-phy@5 {
209 		qsgmii_phy3: ethernet-phy@6 {
213 		qsgmii_phy4: ethernet-phy@7 {
219 		aqr105_phy: ethernet-phy@1 {
220 			compatible = "ethernet-phy-ieee802.3-c45";
228 	ucc_hdlc: ucc@2000 {
229 		compatible = "fsl,ucc-hdlc";
230 		rx-clock-name = "clk8";
231 		tx-clock-name = "clk9";
232 		fsl,rx-sync-clock = "rsync_pin";
233 		fsl,tx-sync-clock = "tsync_pin";
234 		fsl,tx-timeslot-mask = <0xfffffffe>;
235 		fsl,rx-timeslot-mask = <0xfffffffe>;
236 		fsl,tdm-framer-type = "e1";
237 		fsl,tdm-id = <0>;
238 		fsl,siram-entry-id = <0>;
239 		fsl,tdm-interface;