Home
last modified time | relevance | path

Searched +full:tx +full:- +full:freq (Results 1 – 25 of 353) sorted by relevance

12345678910>>...15

/linux/drivers/media/rc/
H A Dite-cir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * skeleton provided by the nuvoton-cir driver.
10 * The lirc_it87 driver was originally written by Hans-Gunter Lutke Uphues
13 * <jimbo-lirc@edwardsclan.net>.
16 * <spmf2004-lirc@yahoo.fr> in 2008.
29 #include <media/rc-core.h>
32 #include "ite-cir.h"
42 static int model_number = -1;
47 /* HW-independent code functions */
50 static inline bool ite_is_high_carrier_freq(unsigned int freq) in ite_is_high_carrier_freq() argument
[all …]
H A Dwinbond-cir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
12 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
26 * o Wake-On-CIR functionality
44 #include <media/rc-core.h>
46 #define DRVNAME "winbond-cir"
48 /* CEIR Wake-Up Registers, relative to data->wbase */
60 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
67 /* SP3 Banked Registers, relative to data->sbase */
71 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
[all …]
/linux/sound/soc/fsl/
H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
[all …]
H A Dfsl_xcvr.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "imx-pcm.h"
78 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
117 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
119 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
130 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
150 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
151 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
162 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
[all …]
H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
57 #define TX 1 macro
66 * (bit-endianness must match byte-endianness). Processors typically write
68 * written in. So if the host CPU is big-endian, then only big-endian
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22 * - HDMI Pixel Clocks generation
26 * - Genenate Pixel clocks for 2K/4K 10bit formats
33 * | | | | | |--ENCI
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
35 * |__________| |_________| \ | MUX |--ENCP
36 * --VCLK2-| |--VDAC
37 * |_____|--HDMI-TX
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
[all …]
/linux/tools/testing/selftests/timers/
H A Dchange_skew.c6 * NOTE: This is a meta-test which cranks the ADJ_FREQ knob and
8 * that the raw_skew, inconsistency-check and nanosleep tests be
12 * $ gcc change_skew.c -o change_skew -lrt
35 struct timex tx; in change_skew_test() local
38 tx.modes = ADJ_FREQUENCY; in change_skew_test()
39 tx.freq = ppm << 16; in change_skew_test()
41 ret = adjtimex(&tx); in change_skew_test()
43 printf("Error adjusting freq\n"); in change_skew_test()
48 ret |= system("./inconsistency-check"); in change_skew_test()
57 struct timex tx; in main() local
[all …]
/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) argument
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
124 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
127 #define TxENAB 0x8 /* Tx Enable */
129 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
130 #define Tx7 0x20 /* Tx 7 bits/character */
[all …]
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
52 #define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) argument
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
142 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
145 #define TxENAB 0x8 /* Tx Enable */
[all …]
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) argument
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
116 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
119 #define TxENAB 0x8 /* Tx Enable */
121 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
122 #define Tx7 0x20 /* Tx 7 bits/character */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
[all …]
/linux/drivers/firmware/arm_scmi/
H A Dperf.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2023 ARM Ltd.
8 #define pr_fmt(fmt) "SCMI Notifications PERF - " fmt
175 if (_opp->indicative_freq == f_) \
203 ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0, in scmi_perf_attributes_get()
208 attr = t->rx.buf; in scmi_perf_attributes_get()
210 ret = ph->xops->do_xfer(ph, t); in scmi_perf_attributes_get()
212 u16 flags = le16_to_cpu(attr->flags); in scmi_perf_attributes_get()
214 pi->num_domains = le16_to_cpu(attr->num_domains); in scmi_perf_attributes_get()
217 pi->power_scale = SCMI_POWER_MILLIWATTS; in scmi_perf_attributes_get()
[all …]
/linux/drivers/net/ethernet/ibm/emac/
H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Register definitions for PowerPC 4xx on-chip ethernet contoller
18 * Copyright 2002-2004 MontaVista Software Inc.
151 #define EMAC4_MR1_OBCI(freq) ((freq) <= 50 ? EMAC4_MR1_OBCI_50 : \ argument
152 (freq) <= 66 ? EMAC4_MR1_OBCI_66 : \
153 (freq) <= 83 ? EMAC4_MR1_OBCI_83 : \
154 (freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
235 #define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \ argument
236 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
237 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
[all …]
/linux/drivers/spi/
H A Dspi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Addy Ke <addy.ke@rock-chips.com>
18 #define DRIVER_NAME "rockchip-spi"
158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
179 const void *tx; member
189 u32 freq; member
196 bool cs_high_supported; /* native CS supports active-high polarity */
203 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); in spi_enable_chip()
212 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) && in wait_for_tx_idle()
213 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) in wait_for_tx_idle()
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dhtt_tx.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
43 struct ath10k *ar = hw->priv; in __ath10k_htt_tx_txq_recalc()
45 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; in __ath10k_htt_tx_txq_recalc()
53 lockdep_assert_held(&ar->htt.tx_lock); in __ath10k_htt_tx_txq_recalc()
55 if (!ar->htt.tx_q_state.enabled) in __ath10k_htt_tx_txq_recalc()
58 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) in __ath10k_htt_tx_txq_recalc()
61 if (txq->sta) { in __ath10k_htt_tx_txq_recalc()
62 arsta = (void *)txq->sta->drv_priv; in __ath10k_htt_tx_txq_recalc()
[all …]
/linux/drivers/net/wireless/marvell/mwifiex/
H A DREADME2 # Copyright 2011-2020 NXP
9 # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
10 # worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
12 # THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
38 Following are some useful iw commands:-
45 iw dev mlan0 connect -w <SSID> [<freq in MHz>] [<bssid>] [key 0:abcde d:1123456789a]
55 iw dev mlan0 ibss join <SSID> <freq in MHz> [fixed-freq] [fixed-bssid] [key 0:abcde]
65 such as SSID, operating frequency, rx/tx packets, signal strength, tx bitrate.
79 mount -t debugfs debugfs /debugfs
98 bss_mode = "Ad-hoc" | "Managed" | "Auto" | "Unknown"
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
163 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
164 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
172 /* 1000BASE-T Control Register */
176 /* 1000BASE-T Status Register */
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
279 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
311 #define IGC_TXD_POPTS_SMD_MASK 0x3000 /* Indicates whether it's SMD-V or SMD-R */
[all …]
/linux/include/sound/
H A Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
[all …]
/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-core.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
79 * [-64,63] for TDCO, indicating a relative TDCO.
115 return __mcp251xfd_get_model_str(priv->devtype_data.model); in mcp251xfd_get_model_str()
160 if (!priv->reg_vdd) in mcp251xfd_vdd_enable()
163 return regulator_enable(priv->reg_vdd); in mcp251xfd_vdd_enable()
168 if (!priv->reg_vdd) in mcp251xfd_vdd_disable()
171 return regulator_disable(priv->reg_vdd); in mcp251xfd_vdd_disable()
177 if (!priv->reg_xceiver) in mcp251xfd_transceiver_enable()
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 IEEE 802.11a/g LP-PHY driver
7 Copyright (c) 2008-2009 Michael Buesch <m@bues.ch>
37 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_lpphy_op_get_default_chan()
48 return -ENOMEM; in b43_lpphy_op_allocate()
49 dev->phy.lp = lpphy; in b43_lpphy_op_allocate()
56 struct b43_phy *phy = &dev->phy; in b43_lpphy_op_prepare_structs()
57 struct b43_phy_lp *lpphy = phy->lp; in b43_lpphy_op_prepare_structs()
60 lpphy->antenna = B43_ANTENNA_DEFAULT; in b43_lpphy_op_prepare_structs()
67 struct b43_phy_lp *lpphy = dev->phy.lp; in b43_lpphy_op_free()
[all …]
/linux/drivers/media/test-drivers/vivid/
H A Dvivid-radio-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * vivid-radio-common.h - common radio rx/tx support functions.
23 int vivid_radio_g_frequency(struct file *file, const unsigned *freq, struct v4l2_frequency *vf);
24 int vivid_radio_s_frequency(struct file *file, unsigned *freq, const struct v4l2_frequency *vf);
H A Dvivid-radio-common.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * vivid-radio-common.c - common radio rx/tx support functions.
13 #include "vivid-core.h"
14 #include "vivid-ctrls.h"
15 #include "vivid-radio-common.h"
16 #include "vivid-rds-gen.h"
56 * is set up with the values from the RDS TX controls, otherwise it
61 struct vivid_rds_gen *rds = &dev->rds_gen; in vivid_radio_rds_init()
62 bool alt = dev->radio_rx_rds_use_alternates; in vivid_radio_rds_init()
65 if (dev->radio_rds_loop && !dev->radio_tx_rds_controls) in vivid_radio_rds_init()
[all …]
/linux/sound/soc/rockchip/
H A Drockchip_i2s_tdm.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
9 #include <linux/clk-provider.h>
23 #define DRV_NAME "rockchip-i2s-tdm"
92 clk_disable_unprepare(i2s_tdm->mclk_tx); in i2s_tdm_disable_unprepare_mclk()
93 clk_disable_unprepare(i2s_tdm->mclk_rx); in i2s_tdm_disable_unprepare_mclk()
97 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
110 ret = clk_prepare_enable(i2s_tdm->mclk_tx); in i2s_tdm_prepare_enable_mclk()
113 ret = clk_prepare_enable(i2s_tdm->mclk_rx); in i2s_tdm_prepare_enable_mclk()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
305 #define E1000_TCTL_EN 0x00000002 /* enable tx */
[all …]

12345678910>>...15