Lines Matching +full:tx +full:- +full:freq
1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
163 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
164 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
172 /* 1000BASE-T Control Register */
176 /* 1000BASE-T Status Register */
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
279 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
311 #define IGC_TXD_POPTS_SMD_MASK 0x3000 /* Indicates whether it's SMD-V or SMD-R */
332 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
336 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
368 #define IGC_RXD_STAT_SMD_TYPE_V 0x01 /* SMD-V Packet */
369 #define IGC_RXD_STAT_SMD_TYPE_R 0x02 /* SMD-R Packet */
414 /* High-priority RX packet buffer size (KB). Used for Express traffic when preemption is enabled */
418 /* Low-priority RX packet buffer size (KB). Used for BE traffic when preemption is enabled */
428 /* Mask for TX packet buffer size */
435 /* TX Packet buffer size in KB */
450 #define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */
451 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
510 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
511 #define IGC_TSYNCTXCTL_TXTT_1 0x00000002 /* Tx timestamp reg 1 valid */
512 #define IGC_TSYNCTXCTL_TXTT_2 0x00000004 /* Tx timestamp reg 2 valid */
513 #define IGC_TSYNCTXCTL_TXTT_3 0x00000008 /* Tx timestamp reg 3 valid */
514 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
519 #define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */
566 #define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
567 #define IGC_TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
571 #define IGC_TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
572 #define IGC_TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
576 #define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
577 #define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
581 #define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
582 #define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
646 #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
653 /* GPY211 - I225 defines */
666 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
667 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
671 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
692 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
693 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
711 /* EEE Link-Partner Ability */
716 #define IGC_N0_QUEUE -1
738 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
747 /* Minimum time for 100BASE-T where no data will be transmit following move out
748 * of EEE LPI Tx state