Lines Matching +full:tx +full:- +full:freq
1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) argument
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
116 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
119 #define TxENAB 0x8 /* Tx Enable */
121 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
122 #define Tx7 0x20 /* Tx 7 bits/character */
123 #define Tx6 0x40 /* Tx 6 bits/character */
124 #define Tx8 0x60 /* Tx 8 bits/character */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
133 #define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */
208 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
215 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
219 #define TxEOM 0x40 /* Tx underrun */
239 /* Read Register 2 (channel b only) - Interrupt vector */
252 #define CHBTxIP 0x2 /* Channel B Tx IP */
255 #define CHATxIP 0x10 /* Channel A Tx IP */
277 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
285 sbus_readb(&channel->data); \
287 sbus_readb(&channel->data); \